Sung-Hyun Lee

Amorphous Silicon Film Deposition by Low Temperature Catalytic Chemical Vapor Deposition (<150 °C) and Laser Crystallization for Polycrystalline Silicon Thin-Film Transistor Application

We deposited amorphous silicon (a-Si) films below 150 °C with a custom-designed catalytic chemical vapor deposition (Cat-CVD) system. The hydrogen content of the films was controlled at less than 1.5 at. %. Excimer laser crystallization was performed without the preliminary dehydrogenation process. Crystallization occurred at a laser energy density above 70 mJ/cm2. Thin-film transistors (TFTs) were fabricated while the entire process temperatures were maintained at below 200 °C. We obtained a field-effect mobility of higher than 100 cm2/(V s) and a sub-threshold slope of 116 mV/dec. The a-Si film prepared by a low temperature Cat-CVD is a promising candidate for polycrystalline silicon TFTs of the active matrix display.

Gate Insulator Inhomogeneity in Thin Film Transistors Having a Polycrystalline Silicon Layer Prepared Directly by Catalytic Chemical Vapor Deposition at a Low Temperature

Polycrystalline silicon (poly-Si) films were prepared directly at a low temperature (<200 °C) by using catalytic chemical vapor deposition (Cat-CVD) technique without subsequent crystallization steps. Top-gate coplanar type thin-film transistors were fabricated using the as-deposited poly-Si films. We obtained a high mobility of ~40 cm2/(V s) and a subthreshold slope of 0.54 V/decade. Instability in threshold voltage with the drain bias could be suppressed by improving the homogeneity in the gate insulator.

Robust Metal/AHO/HSG-Cylinder Capacitor Technology Using Diagonal Cell Array Scheme and Double Mold Oxide

In this paper the novel robust Hemispherical Grain (HSG)-merged Al2O3/HfO2 (AHO) capacitor with diagonal cell array scheme and double mold oxide (DMO) is introduced. The capacitor process with diagonal cell array scheme and double mold oxide can maximize storage node (SN) height up to 2.0 µm in 0.11 µm dynamic random access memory (DRAM) technology by enlarging the bottom size of SN. Also we developed the HSG-merged AHO capacitor for the first time in mass production. The HSG-merged AHO capacitor technique exhibited a capacitance enhancement by 24% without any significant decrease in breakdown voltage compared to Al2O3 (ALO) capacitor.

Erratum: Ion Shower Doping of Polysilicon Films on Polyethersulfone Substrates for Flexible TFT Arrays [ Electrochem. Solid-State Lett. , 9 , H61 (2006) ]

Erratum: Ion Shower Doping of Polysilicon Films on Polyethersulfone Substrates for Flexible TFT Arrays [Electrochem. Solid-State Lett., 9, H61 (2006)] Jongman Kim, Wan-Shick Hong, Sunghyun Lee, Kyung-Bae Park, Do-Young Kim, Ji Sim Jung, Jang-Yeon Kwon, and Takashi Noguchi Samsung Advanced Institute of Science and Technology, San 24 Nongseo-ri, Kiheung-eup, Yongin-city, Kyunggi-do 449-711, Korea Department of Nano Science and Technology, University of Seoul, Seoul 130-743, Korea Department of Electronics Engineering, Sejong University, 98 Kunja-dong, Kwangjin-gu, Seoul 143-747, Korea

Ion shower doping of polysilicon films on polyethersulfone substrates for flexible TFT arrays

A technique of ion shower doping was performed to form source-drain contacts for polysilicon thin-film transistors (TFTs) on polyethersulfone (PES) substrates. The doped layer was subsequently annealed with an excimer laser to electrically activate the dopant atoms. The doped polysilicon films on the PES substrate showed much higher sheet resistances than those on the glass substrate with the identical doping and activation conditions. Moreover, the plastic substrates is easily heated up and caused a film failure for the prolonged exposure of the ion shower doping. The effective doping time and the resulting ion dose could be increased remarkably by reducing the radio-frequency power as well as by inserting interval pulses for dopants relaxation during the ion doping. As a result, a sheet resistance value as low as 300 ohms/sq. was obtained, which is low enough for a good ohmic contact.