Sung-il Cho

Study on the etching characteristics of amorphous carbon layer in oxygen plasma with carbonyl sulfide

Carbonyl sulfide (COS) was added to oxygen as the additive etch gas for etching of amorphous carbon layers (ACL), and its effect on the etching characteristics of ACLs as the etch mask for high aspect ratio contact SiO2 etching was investigated. When a 50 nm amorphous carbon hole was etched in a gas mixture of O2 + 5% COS, not only did the etch profile of the ACL change more anisotropically but also the top/bottom opening ratio of the etch profile was improved by about 37% compared to those etched without COS. The improved ACL etch characteristics were related to the sidewall passivation of the amorphous carbon hole by the carbon sulfide related layer during the etching of the ACL. The distortion of the amorphous carbon hole was also reduced by about 6% due to the uniform deposition of the carbon sulfide related layer on the sidewall of the amorphous carbon hole. This uniform deposition improved the etch profile and opening ratio of the amorphous carbon hole, ultimately resulting in the enhanced contact o...

Atomic layer etching removal of damaged layers in a contact hole for low sheet resistance

A damaged layer remains on silicon substrates after high-aspect-ratio contact (HARC) etching when using a fluorocarbon gas. Atomic layer etching (ALET) is a technique that can be applied to remove the damaged layer of silicon, removing about 1.36 A per etch cycle. The characteristics of contact damage removal by ALET are investigated and compared with the conventional damage removal technique of low-power CF4 plasma etching. The low-power CF4 plasma etching technique not only has inadequate etch depth control, but also introduces secondary damage by implanting impurities about 25 A into the contact bottom of the silicon surface. However, ALET allows contact damage to be removed effectively without introducing secondary damage to the substrate, and with precision etch depth control at the angstrom scale. When ALET is applied subsequent to low-power CF4 plasma etching, the fluorine- and carbon-damaged silicon is effectively removed in about 10 cycles. The sheet resistance of HARC etched silicon decreases fr...

Damaged silicon contact layer removal using atomic layer etching for deep-nanoscale semiconductor devices

Silicon atomic layer etching (ALET) using Cl2 is applied to remove the damaged layer on a 30 nm contact silicon surface formed by high-energy reactive ions during high aspect ratio contact etching, and its effects on the damage removal characteristics are investigated. Compared to a conventional damage removal method, such as the low-power CF4 plasma treatment technique, ALET produces less secondary damage to the substrate and gives exact etch depth control and extremely high etch selectivity to the contact SiO2 insulating pattern mold. When ALET is applied after a conventional damage removal technique, the sheet resistance of the damaged contact silicon surface is improved to a level close to that of a clean silicon surface, while exact atomic-scale depth control is maintained without changes in the pattern mold profile.

Study on contact distortion during high aspect ratio contact SiO2 etching

As pattern density is increased in semiconductor integrated circuits (ICs) and pattern sizes are decreased to nanometer scale, high aspect ratio contact etching has become one of the most difficult processes in nanoscale IC fabrication. The increase in aspect ratio of the contact oxide etching raises problems such as low mask selectivity, microloading, pattern degradation, and etch stops. In this study, the authors investigated the effect of various oxide etch conditions such as mask materials, mask thickness, and oxide etch processes, on contact profile degradation. The results showed that greater contact pattern distortion occurred as the aspect ratio of the etched oxide was increased. The use of amorphous carbon instead of amorphous silicon as the etch mask, and the use of a more carbon-rich gas composition, lessened pattern distortion. The polymer deposited at the interface between the mask layer and the oxide layer appeared to significantly affect the degree of contact pattern distortion. By adding a...

Study on the oxidation and reduction of tungsten surface for sub-50 nm patterning process

The oxidation characteristics of tungsten line pattern during the carbon-based mask-layer removal process using oxygen plasmas have been investigated for sub-50 nm patterning processes, in addition to the reduction characteristics of the WOx layer formed on the tungsten line surface using hydrogen plasmas. The surface oxidation of tungsten lines during the mask layer removal process could be minimized by using low-temperature (300 K) plasma processing for the removal of the carbon-based material. Using this technique, the thickness of WOx on the tungsten line could be decreased to 25% compared to results from high-temperature processing. The WOx layer could also be completely removed at a low temperature of 300 K using a hydrogen plasma by supplying bias power to the tungsten substrate to provide a activation energy for the reduction. When this oxidation and reduction technique was applied to actual 40-nm-CD device processing, the complete removal of WOx formed on the sidewall of tungsten line could be ob...

METAL-INSULATOR TRANSITIONS IN POLYCRYSTALLINE VOx THIN FILMS

ABSTRACT Metal-insulator transition properties in polycrystalline VOx thin films, which were deposited using rf magnetron sputtering with a vanadium target on Pt/Ti/SiO2/Si substrates, were studied in terms of structural and electrical characteristics. The phase change of VOx thin films by annealing was confirmed from amorphous VOx films to mixed crystalline phases containing V2O3,VO2,V6O13, and V2O5. The metal-insulator transition of VOx thin films was observed by current-voltage measurement as a function of top-electrode area and the temperature. It was demonstrated that the VOx thin films can be applied to memory devices employing the transition from a high-resistance (off) insulating state to a low-resistance (on) metallic state.

Robust single chip on screen display for home VCRs

This paper describes the design of a robust on-screen-display (OSD) chip with improved automatic frequency control (AFC). The built-in AFC reduces the amount of sync jitter caused by the VCR head switching pulse, video copy guard signals, etc. This chip contains the OSD circuitry which can display characters of up to 12 rows by 30 columns on display systems. The character colors can be changed by programming the content of an 8-bit control register through the serial interface. It also provides the functions of half tone, box drawing, scroll, and blink. The chip was fabricated by using a 0.65 /spl mu/m double metal CMOS process.