In-kyeong Yoo

A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O5−x/TaO2−x bilayer structures

Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaO(x)-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 10(12). Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.

Graphene Barristor, a Triode Device with a Gate-Controlled Schottky Barrier

Updating the Triode with Graphene In early electronics, the triode—a vacuum device that combined a diode and an electrical grid—was used to control and amplify signals, but was replaced in most applications by solid-state silicon electronics. One characteristic of silicon-metal interfaces is that the Schottky barrier created—which acts as a diode—does not change with the work function of the metal—the Fermi level is pinned by the presence of surface states. Yang et al. (p. 1140, published online 17 May) now show that for a graphene-silicon interface, Fermi-level pinning can be overcome and a triode-type device with a variable barrier, a “barristor,” can be made and used to create devices such as inverters. The absence of defects and surface oxides at a graphene/silicon interface enables voltage control of graphene devices. Despite several years of research into graphene electronics, sufficient on/off current ratio Ion/Ioff in graphene transistors with conventional device structures has been impossible to obtain. We report on a three-terminal active device, a graphene variable-barrier “barristor” (GB), in which the key is an atomically sharp interface between graphene and hydrogenated silicon. Large modulation on the device current (on/off ratio of 105) is achieved by adjusting the gate voltage to control the graphene-silicon Schottky barrier. The absence of Fermi-level pinning at the interface allows the barrier’s height to be tuned to 0.2 electron volt by adjusting graphene’s work function, which results in large shifts of diode threshold voltages. Fabricating GBs on respective 150-mm wafers and combining complementary p- and n-type GBs, we demonstrate inverter and half-adder logic circuits.

Electrical manipulation of nanofilaments in transition-metal oxides for resistance-based memory.

The fabrication of controlled nanostructures such as quantum dots, nanotubes, nanowires, and nanopillars has progressed rapidly over the past 10 years. However, both bottom-up and top-down methods to integrate the nanostructures are met with several challenges. For practical applications with the high level of the integration, an approach that can fabricate the required structures locally is desirable. In addition, the electrical signal to construct and control the nanostructures can provide significant advantages toward the stability and ordering. Through experiments on the negative resistance switching phenomenon in Pt-NiO-Pt structures, we have fabricated nanofilament channels that can be electrically connected or disconnected. Various analyses indicate that the nanofilaments are made of nickel and are formed at the grain boundaries. The scaling behaviors of the nickel nanofilaments were closely examined, with respect to the switching time, power, and resistance. In particular, the 100 nm x 100 nm cell was switchable on the nanosecond scale, making them ideal for the basis for high-speed, high-density, nonvolatile memory applications.

2-stack 1D-1R Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications

We have successfully integrated a 2-stack 8times8 array 1D- lR (one diode-one resistor) structure with 0.5 mumtimes0.5 mum cells in order to demonstrate the feasibility of high density stacked RRAM. p-CuOx/n-InZnOx heterojunction thin film was used for the first time as a oxide diode which shows increased current density of two orders over our previous p-NiOx/n-TiOx oxide diode. And Ti-doped NiO was used for the storage node. No limitation to the number of stacks has been observed from our results. Cell and device properties of our cross-point structure 8times8 array are reported. In addition, all fabrication processes were done at room temperature without other dedicated facilities or processes allowing for compatibility with current CMOS technology. Bi-stable switching for 1D-1R memory was demonstrated for our 2-stack cross-point structures showing excellent behavior for both diode and storage nodes. The forward current density for p-CuOx/n-IZOx diodes was over 104A/cm2, and the operation voltage for the storage node with diode attached was around 3 V.

Physical electro-thermal model of resistive switching in bi-layered resistance-change memory

Tantalum-oxide-based bi-layered resistance-change memories (RRAMs) have recently improved greatly with regard to their memory performances. The formation and rupture of conductive filaments is generally known to be the mechanism that underlies resistive switching. The nature of the filament has been studied intensively and several phenomenological models have consistently predicted the resistance-change behavior. However, a physics-based model that describes a complete bi-layered RRAM structure has not yet been demonstrated. Here, a complete electro-thermal resistive switching model based on the finite element method is proposed. The migration of oxygen vacancies is simulated by the local temperature and electric field derived from carrier continuity and heat equations fully coupled in a 3-D geometry, which considers a complete bi-layered structure that includes the top and bottom electrodes. The proposed model accurately accounts for the set/reset characteristics, which provides an in-depth understanding of the nature of resistive switching.

Resistance-switching Characteristics of polycrystalline Nb/sub 2/O/sub 5/ for nonvolatile memory application

The resistance switching characteristics of polycrystalline Nb/sub 2/O/sub 5/ film prepared by pulsed-laser deposition (PLD) were investigated for nonvolatile memory application. Reversible resistance-switching behavior from a high resistance state to a lower state was observed by voltage stress with current compliance. The reproducible resistance-switching cycles were observed and the resistance ratio was as high as 50-100 times. The resistance switching was observed under voltage pulse as short as 10 ns. The estimated retention lifetime at 85/spl deg/C was sufficiently longer than ten years. Considering its excellent electrical and reliability characteristics, Nb/sub 2/O/sub 5/ shows strong promise for future nonvolatile memory applications.

Decrease in switching voltage fluctuation of Pt∕NiOx∕Pt structure by process control

Resistance change random access memory devices using NiOx films with resistance switching properties have immense potential for high-density nonvolatile memory exceeding currently used flash memory. The only critical failure of a NiOx film is to write wrong information due to large fluctuations of switching voltages during successive resistance switching operations. The authors show that failure-free NiOx film can be grown directly on Pt electrode just by process control. Intensive analyses show that the superior resistance switching behaviors of their simple Pt∕NiOx∕Pt structure may result from a very thin Ni–Pt layer self-formed at the bottom interface during deposition of NiOx.

Multi-level switching of triple-layered TaOx RRAM with excellent reliability for storage class memory

A highly reliable RRAM with multi-level cell (MLC) characteristics were fabricated using a triple-layer structure (base layer/oxygen exchange layer/barrier layer) for the storage class memory applications. A reproducible multi-level switching behaviour was successfully observed, and simulated by the modulated Schottky barrier model. Morevoer, a new programming algorithm was developed for more reliable and uniform MLC operation. As a result, more than 107 cycles of switching endurance and 10 years of data retention at 85°C for all the 2 bit/cell operation were archieved.

A plasma-treated chalcogenide switch device for stackable scalable 3D nanoscale memory

Stackable select devices such as the oxide p-n junction diode and the Schottky diode (one-way switch) have been proposed for non-volatile unipolar resistive switching devices; however, bidirectional select devices (or two-way switch) need to be developed for bipolar resistive switching devices. Here we report on a fully stackable switching device that solves several problems including current density, temperature stability, cycling endurance and cycle distribution. We demonstrate that the threshold switching device based on As-Ge-Te-Si material significantly improves cycling endurance performance by reactive nitrogen deposition and nitrogen plasma hardening. Formation of the thin Si₃N₄ glass layer by the plasma treatment retards tellurium diffusion during cycling. Scalability of threshold switching devices is measured down to 30 nm scale with extremely fast switching speed of ~2 ns.

Graphene for true Ohmic contact at metal-semiconductor junctions.

The rectifying Schottky characteristics of the metal-semiconductor junction with high contact resistance have been a serious issue in modern electronic devices. Herein, we demonstrated the conversion of the Schottky nature of the Ni-Si junction, one of the most commonly used metal-semiconductor junctions, into an Ohmic contact with low contact resistance by inserting a single layer of graphene. The contact resistance achieved from the junction incorporating graphene was about 10(-8) ~ 10(-9) Ω cm(2) at a Si doping concentration of 10(17) cm(-3).