Sung-Joon Jang

Hardware implementation of fast high dynamic range processor for real-time 4K UHD video

The high dynamic range (HDR) has become very important because of the rapid increase in demand for a variety of applications. However, most of them were implemented by expensive systems due to the high complex computation for processing the real-time 4K UHD video. In the proposed hardware, the non-linear camera response function (CRF) with the area optimization of logarithmic computations has been applied to improve HDR quality. And, for embedding in Field Programmable Gate Array (FPGA), we implement a dedicated hardware using 4006 lookup table (LUT) and 21KB sized internal memory. The proposed architecture enables a real-time HDR processing with pipelining for a UHD video (8 Mega pixels) at 30 frames per second.

Hardware implementation of fast traffic sign recognition for intelligent vehicle system

In intelligent vehicle systems, the traffic sign recognition (TSR) has become very important because of the rapid increase in demand of intelligent transportation system (ITS). However, most of them were implemented by expensive systems due to the high complex computation for processing the real-time segmentation and recognition process. In this paper, the preprocessing with the red region extraction in the RGB color space has been applied to improve TSR performance. To implement proposed architecture, we adopt the Xilinx Virtex-7 V2000T Field Programmable Gate Array (FPGA) with a fully pipelined structure. Experimental results show that the implemented preprocessing block use 1,212 lookup table (LUT) and 11.14 KB sized internal memory. The proposed architecture enables a real-time TSR processing with pipelining for a full-HD (FHD) video (2 Mega pixels) at 60 frames per second.

Memory optimization of bilateral filter and its hardware implementation

As a method for edge-preserving or noise-reducing, a bilateral filter is widely used. However, because every pixel in a filtering window needs a separate Look-Up Table (LUT) for the parallel processing, its hardware implementation is still bulky. In this paper, we propose Similar Weight Grouping (SWG) which maps multiple indexes with a similar value onto a single index and Zero Value Suppression (ZVS) which removes indexes with a value of almost zero to reduce a size of the LUT. By our scheme, a total size of LUT is reduced by approximately 95% while maintaining its performance. Finally, it is implemented using 7.7 KB on-chip memory and 93.1 Kgates with 65 nm process.

Hardware feasibility analysis for motion segmentation initialization

We analyze and evaluate different initialization methods for motion layers segmentation, a powerful mid-level vision tool. We estimate 6-D affine motion models from the optical flow corresponding to different over-segmentations. Over-segmentations can be either uniform rectangular blocks; or adaptive sized rectangular blocks; or super-pixels; or based on any other clustering methods. We present performance analysis of motion segmentation initialization algorithms on video sequences and discuss the relative pros and cons of these methods in terms of hardware implementation issues.