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Dive into the research topics where Sung-Kwon Lee is active.

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Featured researches published by Sung-Kwon Lee.


Journal of Vacuum Science and Technology | 2009

Dry etching of CoFe films using a CH4∕Ar inductively coupled plasma for magnetic random access memory application

Doo-Seung Um; Dong-Pyo Kim; Jong-Chang Woo; Chang-Il Kim; Sung-Kwon Lee; Tae-Woo Jung; Seung-Chan Moon

In this study, the CoFe thin film was studied using an inductively coupled plasma system in CH4-based gas chemistries. The etch rate of the CoFe thin film was systemically studied by the process parameters including the gas mixing ratio, the rf power, the dc-bias power, and the process pressure. The best gas composition for etching was in CH4 (20%)/Ar (80%) ratio. As the rf power and the dc-bias voltage were increased, the etch rate of the CoFe thin film increased in a CH4∕Ar inductively coupled plasma system. The best process pressure condition for etching was 10mTorr in the CH4∕Ar inductively coupled plasma system. The changes in the components on the surface of the CoFe thin film were investigated with energy dispersive x ray.


Applied Physics Letters | 2002

Formation mechanism of the multilayered-structure barrier of WNx/Si(100)

Ilsang Choi; Jungwoo Park; Joungcheul Choi; Hyung-Chul Kim; Sung-Kwon Lee

The chemical bonding states, microstructure, and the formation mechanism of an interfacial layer between WNx/Si(100) treated by rapid thermal annealing at various temperatures were investigated. It was found that the ultrathin interfacial layer had the multilayered structure of SiO2/SiOxNy/nano-WSi2. The interfacial silicon nitride layer formed by lower annealing temperatures was converted into an oxide layer by increasing the annealing temperature. The thickness of the interfacial oxide layer increased from ∼34 to ∼50 A with the annealing temperature. It was found that the interfacial layer played a role as a barrier against silicidation between W and Si(100) up to 1000 °C.


Proceedings of SPIE, the International Society for Optical Engineering | 2006

Development of multi-function hard mask to simplify process step

Kilyoung Lee; Samyoung Kim; Geunsu Lee; Sung-Kwon Lee; Junhee Cho; Won-Kyu Kim; Cheol-Kyu Bok; Hyeong-Soo Kim; Seung-Chan Moon; Jin-Woong Kim

ArF lithography has been driven into sub-100 nm dimensions using high numerical apertures, phase-shift mask, modified illumination, and optical proximity correction. As feature size continues to shrink, photoresist thickness as an imaging layer has been decreased for the improvement of lithographic process window and pattern collapse margin. Moreover, ArF photoresist has the inherent demerit of poor etch resistance in comparison with KrF photoresist and we have to use inorganic hard mask materials such as silicon-nitride, -oxide, poly-silicon, and silicon oxynitride as a pattern transfer layer. The cost-of-ownership (COO) of CVD process related to the application of inorganic hard mask is much more expensive than that of spin-on process. Therefore, several processes including bi-layer resist process (BLR), and tri-layer resist process (TLR)1 have been investigated. This paper will focus on TLR process consisted of multi-function hard mask (MFHM) material and spin on carbon (SOC) material.


Proceedings of SPIE | 2007

Optimization of material and process parameter for minimizing defect in implementation of MFHM process

Kilyoung Lee; Junggun Heo; Keundo Ban; Hyungsuk Seo; Geunsu Lee; Won-Kyu Kim; Junhee Cho; Jun-Hyeub Sun; Sung-Kwon Lee; Cheol-Kyu Bok; Seung-Chan Moon; Jin-Woong Kim

Silicon-containing material has recently attracted attention as new hard mask material. We have studied the applicability of MFHM (Multi-Functional Hard Mask)/SOC (Spin on Carbon) materials as an alternative to the BARC/SiON/ amorphous carbon (a-C) process. This process is very useful in terms of cost reduction and process simplicity compared to a-C process. Evaluation results have showed good lithographic and etch performances. However, this MFHM process has showed specific defects related to material. This paper will focus on defect type and suggest its solution.


Archive | 2002

Method for fabricating semiconductor device capable of covering facet on plug

Sung-Kwon Lee; Min-Suk Lee; Sang-Ik Kim; Chang-Youn Hwang; Weon-Joon Suh


Archive | 2003

Method for fabricating semiconductor device with fine patterns

Sung-Kwon Lee; Sang-Ik Kim; Min-Suk Lee


Archive | 2004

Method for fabricating semiconductor device with improved tolerance to wet cleaning process

Sung-Kwon Lee; Min-Suk Lee


Archive | 2004

Method and fabricating semiconductor device

Min-Suk Lee; Sung-Kwon Lee


Archive | 2004

Method for fabricating semiconductor device capable of preventing damage by wet cleaning process

Sung-Kwon Lee; Min-Suk Lee


Archive | 2003

Method for fabricating semiconductor device capable of reducing seam generations

Hyeok Su Kang; Sung-Kwon Lee; Min-Suk Lee

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