Sung-Soo Choi
Samsung
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Publication
Featured researches published by Sung-Soo Choi.
symposium on vlsi technology | 2005
Soon-Hong Ahn; Y.N. Hwang; Y.J. Song; S.H. Lee; S.Y. Lee; J.H. Park; Changbum Jeong; K.C. Ryoo; J.M. Shin; Y. Fai; Jae-joon Oh; Gwan-Hyeob Koh; G.T. Jeong; Suk-ho Joo; Sung-Soo Choi; Yong-Hoon Son; Jungyeop Shin; Y.T. Kim; H.S. Jeong; Kinam Kim
Novel small contact fabrication technologies were proposed to realize reliable high density 256Mb PRAM(phase change memory) product. Introducing the 2-step CMP (chemical mechanical polishing) process and the ring-shaped contact structure, the contact area distribution was greatly improved even at the smallest contact diameter of 50nm node. The validity of this approach was directly confirmed by the evaluation of the functionality for the fabricated 256Mbit PRAM based on 0.10/spl mu/m CMOS technology.
symposium on vlsi technology | 2002
Sung-Soo Choi; B.Y. Nam; J.-H. Ku; Dong-Chan Kim; Se-Hoon Lee; J.J. Lee; J.W. Lee; J.D. Ryu; S.J. Heo; J.K. Cho; S.P. Yoon; C.J. Choi; Y.J. Lee; J.H. Chung; B.H. Kim; M.B. Lee; Gil Heyun Choi; Yun-Hee Kim; K. Fujihara; U-In Chung; Joo Tae Moon
Sub-100 nm DRAM is successfully fabricated for the first time with several key technologies, including W/W/sub x/N-poly gate, bitline structure having low parasitic capacitance, Ru/Ta/sub 2/O/sub 5//poly-Si capacitor and advanced CVD-Al contact processes. A fully functional working device is obtained with promising cell performance. Each technology also shows its extendibility as a manufacturable module process for further scaled DRAM.
symposium on vlsi technology | 2017
Sung-Soo Choi; Kyung-Ho Lee; Jungbin Yun; Sung-Ho Choi; Seungjoon Lee; Jung-Hoon Park; Eun Sub Shim; Junghyung Pyo; Bum-Suk Kim; Min-wook Jung; Y. J. Lee; Kyungmok Son; Sang-il Jung; Tae-Shick Wang; Yun-seok Choi; Dong-Ki Min; Joonhyuk Im; Chang-Rok Moon; Duck-Hyung Lee; Duckhyun Chang
We present a CMOS image sensor (CIS) with phase detection auto-focus (PDAF) in all pixels. The size of photodiode (PD) is 0.64μm by 1.28μm, the smallest ever reported and two PDs compose a single pixel. Inter PD isolation was fabricated by deep trench isolation (DTI) process in order to obtain an accurate AF performance. The layout and depth of DTI was optimized in order to eliminate side effects and maximize the performance even at extremely low light condition up to 1lux. In particular the AF performance remains comparable to that of 0.70μm dual PD CIS. By using our unique technology, it seems plausible to scale further down the size of pixels in dual PD CIS without sacrificing AF performance.
international symposium on electromagnetic compatibility | 2017
Soonyong Lee; Yeonsik Yu; Hoyong Kim; Yonghee Cho; Sung-Soo Choi
In this paper, to estimate the Wi-Fi throughput between smart TV and AP (Access Point), the novel methodology is realized by modeling of Wi-Fi 802.11n communication considered real system characteristics. Also, analysis of throughput performance of digital TV by noise effect using the simulation methodology is presented. This result shows very good agreement between measurement and the proposed methodology.
Archive | 2013
June-Woo Lee; Jae-Beom Choi; Kwan-Wook Jung; Sung-Soo Choi; Seong-Jun Kim; Guang-Hai Jin; Ga-Young Kim; Jee-Hoon Kim
Archive | 2012
June-Woo Lee; Jae-Beom Choi; Kwan-Wook Jung; Sung-Soo Choi; Seong-Jun Kim; Guang-Hai Jin; Ga-Young Kim; Jee-Hoon Kim
Archive | 2012
June-Woo Lee; Jae-Beom Choi; Kwan-Wook Jung; Sung-Soo Choi; Seong-Jun Kim; Guang-Hai Jin; Ga-Young Kim; Jee-Hoon Kim
Archive | 2014
Jae Sung Shin; Min-Seok Oh; Sung-Soo Choi; Hyoung-soo Ko; Taechan Kim
symposium on vlsi technology | 2000
Ja Hum Ku; C.-J. Choi; S. Song; Sung-Soo Choi; K. Fujihara; Ho Kyu Kang; S.I. Lee; H. G. Choi; D. H. Ko
Archive | 2013
June-Woo Lee; Jae-Beom Choi; Kwan-Wook Jung; Sung-Soo Choi; Seong-Jun Kim; Guang-Hai Jin; Ga-Young Kim; Jee-Hoon Kim