K. Fujihara

Effect of polysilicon gate on the flatband voltage shift and mobility degradation for ALD-Al/sub 2/O/sub 3/ gate dielectric

Al/sub 2/O/sub 3/ (EOT=22.7 /spl Aring/) gate dielectric layer formed by Atomic Layer Deposition (ALD) process have been characterized for sub-100 nm CMOS devices. The gate leakage current was 3 orders of magnitude lower than that of SiO/sub 2/ and the hysteresis of C-V curve was not observed. However, the negative fixed charge induced the flat band voltage (Vfb) shift and degraded the channel mobility of MOS transistor. The Vfb shift was reduced and channel mobility was improved by applying P+ gate by BF/sub 2/ implantation. It is suggested that the phosphorous diffused from gate polysilicon has a role of network modifier in Al/sub 2/O/sub 3/ film and formation of the Al-O- dangling bond which may be ascribed to negative fixed charge.

A novel SiGe-inserted SOI structure for high performance PDSOI CMOSFETs

A novel partially-depleted silicon-on-insulator (PDSOI) CMOSFETs with SiGe-inserted layer have been proposed. The SiGe-inserted layer in NMOS successively suppresses the floating body effects (FBE) by lowering the body-to-source potential barrier to hole current. It also provides a good current performance in PMOS by inducing the change of channel dopant distribution and increasing the efficiency of pocket ion implantation. Consequently, SiGe-inserted SOI devices achieve higher drain-to-source breakdown voltage in NMOS due to the suppression of FBE and increase drive currents of both NMOS and PMOS by 10% and 15%, respectively, compared to conventional PDSOI devices.

CMOS device scaling beyond 100 nm

CMOS device scaling beyond 100 nm has been investigated. Issues on scaling and previous works to solve them were reviewed. Super steep retrograde channel formation using selective epitaxial growth of undoped silicon effectively suppressed short channel effect and improved transconductance. The stack gate dielectrics of oxynitride and nitride suppressed boron penetration and improved drive currents. Transistor characteristics and reliability issues on gate oxide scaling were investigated in the regime of large gate leakage currents. High performance CMOS transistors of L/sub gate/=70 nm and T/sub ox/=1.4 nm were fabricated, which showed current drives of 860 /spl mu/A//spl mu/m (NMOS) and 350 /spl mu/A//spl mu/m (PMOS) at I/sub off/=10 nA//spl mu/m and V/sub dd/=1.2 V.

Void free and low stress shallow trench isolation technology using P-SOG for sub 0.1 /spl mu/m device

Highly reliable void free shallow trench isolation (VF-STI) technology by employing polysilazane based inorganic spin-on-glass (P-SOG) is developed for sub-0.1 /spl mu/m devices. In order to overcome the difficulties from the gap-filling and accumulated mechanical stress in STI, a P-SOG pillar is introduced at the trench bottom. As a result, the P-SOG pillar, having low stress, improves data retention time and hot carrier immunity in 256 Mbit DRAM by reducing cumulative STI stress. In addition, VF-STI shows an excellent extendibility in terms of gap filling capability even at an aspect ratio of more than 10 without void formation.

On the gate oxide scaling of high performance CMOS transistors

The gate oxide scalability of high performance CMOS transistor has been investigated. In terms of gate leakage, the T/sub ox/ can be scaled down to at least 8 /spl Aring/ with I/sub G/ not exceeding I/sub off/ limit suggested by ITRS. To reduce boron penetration, remote-plasma-nitridation (RPN) oxides were studied. Devices with RPN oxides showed excellent resistance against boron penetration, improved hole mobility, reduced gate leakage, and improved transistor performance. The gate oxide scalability can be extended using the RPN process.

High performance pMOSFET with BF/sub 3/ plasma doped gate/source/drain and S/D extension

A BF/sub 3/ Plasma doping (PLAD) process has been utilized in source/drain/gate and shallow S/D extension for high performance 0.18 /spl mu/m pMOSFET. Gate oxide reliability, drain current, and transconductance of the pMOSFET with BF/sub 3/ PLAD are remarkably improved compared to those of BF/sub 2/ ion implanted devices. Cobalt salicide formation is also compatible with the plasma doped S/D junction.

Elimination of Al Line and Via Resistance Degradation under HTS Test in Application of F-Doped Oxide as Intermetal Dielectric.

Fluorine-doped silicon oxide (SiOF) as intermetal dielectric (IMD) layer was deposited by conventional plasma-enhanced chemical vapor deposition (CVD). The main issues in the application of SiOF as IMD are as follows: (1) instability of film properties such as stress and refractive index during HTS test, (2) desorption of H 2 O and HF gases from SiOF film, (3) increase of line resistance, (4) wedgelike defects of metal lines, and (5) via resistance degradation during HTS test at 350°C. The above problems in use of SiOF as IMD can be eliminated by the passivation of IMD with PE-SiN and the application of Ti underlayer before the second metal deposition.

Design of sub-100 nm CMOSFETs: gate dielectrics and channel engineering

Sub-100 nm CMOS transistors with ultra-thin gate dielectrics below 2.0 nm were fabricated and characterized. Super-steep retrograde channel profiles using boron (NMOS) or arsenic (PMOS) channel implantation followed by selective epitaxial growth of undoped-Si were found to effectively reduce short-channel effect and improve current drivability even in the sub-100 nm regime. For NMOS, indium implanted devices showed better short-channel immunity, however, no improvement in current drivability was observed. Optimization of the gate oxide thickness versus gate length was investigated in the presence of direct tunneling leakages and for the first time, an experimental guideline of oxide scaling is proposed. For PMOS, to suppress boron penetration, sub-2.0 nm stack gate dielectrics of oxynitride and LPCVD nitride were developed, which showed excellent transistor characteristics.

High Thermal Stability of Ni Monosilicide from Ni-Ta Alloy Films on Si(100)

We investigated the thermal stability of NiSi using Ni-Ta alloy films on Si(100) substrate. After silicidation using one-step rapid thermal processing (RTP) at 500°C for 30 s, uniform NiSi layers were formed from both Ni/Si and Ni-Ta/Si systems. To compare thermal stability of NiSi formed by RTP at 500°C, an additional annealing was performed in a furnace at 600°C for 120 min after a self-aligned silicide (SALICIDE) process. In the Ni-Ta/Si system, the silicide layer exhibited a NiSi phase and a stable sheet resistance of 5 Ω/□ even after furnace annealing at 600°C for 120 min. In the Ni/Si system, however, the sheet resistance dramatically increased with an increase of annealing time due to phase transition from NiSi to NiSi 2 . X-ray diffraction data and transmission electron microscopy images also suggest that the thermal stability of NiSi was remarkably improved by addition of Ta. In addition, it is confirmed that Ni 0 . 9 0 Ta 0 . 1 0 film does not react with any dielectric materials (SiO 2 ,Si 3 N 4 ) at an annealing temperature of 500°C. Conclusively, the experimental results strongly suggest that Ni-Ta film could be applicable to high performance sub-0.1 μm devices for SALICIDE processes. 10.1149/1.1601813]. All rights reserved.

Highly manufacturable sub-100 nm DRAM integrated with full functionality

Sub-100 nm DRAM is successfully fabricated for the first time with several key technologies, including W/W/sub x/N-poly gate, bitline structure having low parasitic capacitance, Ru/Ta/sub 2/O/sub 5//poly-Si capacitor and advanced CVD-Al contact processes. A fully functional working device is obtained with promising cell performance. Each technology also shows its extendibility as a manufacturable module process for further scaled DRAM.