Sung-Wan Hong

A 40 mV Transformer-Reuse Self-Startup Boost Converter With MPPT Control for Thermoelectric Energy Harvesting

This paper presents transformer-based self-starting boost converter architecture with low-power maximum power point tracking (MPPT) control for low-voltage thermoelectric generator applications. The minimum working voltage of the proposed boost converter is 40 mV with oscillation through a positive feedback loop formed by a native MOS and transformer. The oscillation autonomously starts up by thermal noise and VOUT is charged up to 1.2 V by the oscillation so that the control block can operate. After that, the transformer for start-up is reused as an inductor, and the normal boost converter mode is enabled for better energy transfer efficiency. An improved MPPT sensing method is also proposed to simplify the circuit. The prototype chip is implemented in a 0.13-μm CMOS process. It operates with an input voltage range of 40 mV to 300 mV and provides a maximum output power of 2.7 mW with a maximum efficiency of 61% at an output voltage of 2 V.

High-Gain Wide-Bandwidth Capacitor-Less Low-Dropout Regulator (LDO) for Mobile Applications Utilizing Frequency Response of Multiple Feedback Loops

This paper presents a novel capacitor-less low-dropout regulator (LDO) for mobile applications. The proposed capacitor-less LDO utilizes multiple feedback loops to satisfy several design challenges for some mobile applications which were not considered in the previous capacitor-less LDOs. The proposed LDO has a wide bandwidth of 3.03 MHz at a load current of 150 mA with a bias current of 40 μA, and the best line and load regulations of 0.0024%/V and 0.0000417%/mA, respectively, which are improvements over previously reported LDOs. This chip has a 100 mV dropout voltage with a 150 mA maximum load current. A total capacitance of 29 pF was used with a chip size of 0.279 mm2.

Zero-order control of boost DC-DC converter with transient enhancement using residual current

A variety of controllers are used in DC-DC converters. Among them, voltage-mode control and current-programmed-mode control are widely used in industrial applications. In such controllers, however, values of inductor, output capacitor, and/or load condition usually affect loop stability and limit the performance of switching converter. Recently, load-independent-control (LIC) method is reported, where freewheeling current is fed back to overcome such a limitation [1]. While this is a viable solution in principle, it still has a vulnerable aspect that must be addressed: the feedback control is affected by the level of freewheeling current and an extra power switch is needed for freewheeling current flow which lowers power efficiency. Another LIC method using vestigial current control is reported in [2]. The weak points of vestigial control are that it needs an auxiliary output and power is consumed in steady state to regulate vestigial current. In this paper, we present a zero-order-controlled (ZOC) boost DC-DC converter that has a robust control loop and does not consume any extra power in the steady state.

High Area-Efficient DC-DC Converter With High Reliability Using Time-Mode Miller Compensation (TMMC)

This paper presents a novel on-chip compensation scheme, the Time-Mode Miller Compensation (TMMC), for DC-DC converter in which the compensation components are integrated on-chip. Using this proposed scheme, the DC-DC converter is stably compensated and insensitive to process variations, with significantly small compensation components ( 1 pF and 80 kΩ in this work) consuming very small silicon area owing to the characteristic of the TMMC. The small compensation components make the chip size small, with 0.12 mm2 of core area (w/o power transistors) using 0.18 μm I/O process. This core size is as small as that of the digital DC-DC converters implemented with less than sub-50 nm process. The measurement result shows that the maximum power efficiency of 90.6% is obtained at the load current of 220 mA with the switching frequency of 1.15 MHz when the input and the output voltages are 3.3 V and 2 V, respectively.

High area-efficient DC-DC converter using Time-Mode Miller Compensation (TMMC)

For the controller design of a DC-DC converter, a Time-Mode Miller Compensation (TMMC) is introduced in this paper. Using this concept, the consuming area of the DC-DC converter can be significantly reduced without any off-chip compensation components. The chip is implemented in 0.18μm I/O CMOS whose size is similar to 0.35μm CMOS, and the core size of this work is only 0.12mm2. Peak efficiency is 90.6%, with switching frequency of 1.15MHz.

Enhanced exchange coupling constant and thermal stability of antiferromagnetically coupled media with thin Co interlayers

The magnetic properties and thermal stability of antiferromagnetically coupled (AFC) media with thin Co interlayers are investigated. Since the thermal stability is strongly dependent on the exchange coupling constant Jex in the AFC media, the thin Co interlayers were inserted on both interfaces of the Ru layer to obtain higher values of Jex. The Jex above 0.6 erg/cm2 was obtained in the AFC media with the Co interlayers above 1 nm in comparison with about 0.1 erg/cm2 in AFC media without the Co interlayers. The thermal stability of the AFC media with Co interlayers was greatly improved over those of the AFC media without Co interlayers.

Zero

This paper proposes a new control scheme of zeroth-order control (ZOC) for PWM DC-DC converters in which the pole frequencies of the control loop are no longer dependent on the values of the inductor, output capacitor, or the output load current. In the proposed scheme, the output voltage of the converter is regulated by a comparator. The main control loop of the converter regulates the inductor energy which is built up to an optimum value to be delivered to the output by means of the time interval between the rising edge of the main switch driving pulse and the comparator output pulse. A boost DC-DC converter with the proposed ZOC has been implemented and fabricated in a commercial 0.35 μm BCDMOS process. A maximum efficiency of 88% is achieved at a total output power of 480 mW with the switching frequency of 833 kHz when the input voltage and the output voltage are 3.7 V and 8 V, respectively. Over 85% efficiency is maintained for a wide range of the output load current from 40 mA to 300 mA.

^{\rm th}

Herein we propose a new PWM controller for a DC-DC converter with a Self-aligned Comparator Control (SCC), the purpose of which is to overcome sub-harmonic switching and hysteretic characteristics that are problematic in conventional comparator control schemes. In the proposed scheme, the condition of the output voltage is converted to the form of a phase difference through the SCC block. The main control loop of the converter regulates the inductor current which is built up to an optimum value by using this phase difference. In addition to the SCC, the proposed PWM controller is fully integrated on-chip without off-chip components to decrease the size and cost of the DC-DC converter using a new Switching Noise Robust Charge-pump (SNRC). A boost DC-DC converter with the proposed SCC and SNRC was designed and fabricated in a commercial 0.35 μm BCDMOS process with total controller area of 0.791 mm2 . A maximum efficiency of 90% was achieved at a total output power of 480 mW with a switching frequency of 926 kHz when the input and the output voltages were 3.7 V and 8 V, respectively. Over 85% efficiency was maintained over a wide range of output load current from 40 mA to 300 mA.

-Order Control of Boost DC-DC Converter With Transient Enhancement Scheme

An envelope modulator (EM) is presented to increase the efficiency of an RF power amplifier. In order to supply an output voltage higher than the input voltage while providing low-frequency power in the EM, a single-inductor dual-output (SIDO) converter is introduced. By employing the SIDO converter, the EM does not require an additional boost converter. In addition, a high-frequency converter (HFC) with a wide-bandwidth capability is also proposed. These two converters, the SIDO converter and the HFC, are combined in parallel without an ac coupling capacitor by employing a low-frequency current-balancing technique. The chip is implemented in a 0.18-μm CMOS process and achieves 86.5% peak efficiency while tracking a 10-MHz long-term evolution envelope signal.

A 0.791 mm

For achieving boost capability and wideband with high efficiency in Envelope Modulator (EM), a newly proposed topology is introduced in this paper. The proposed EM consists of two converters: one is Low Frequency Converter (LFC) with Single Inductor Dual Output (SIDO) and the other is High Frequency Converter (HFC) with wideband capability. The two converters are combined directly in parallel without AC coupling capacitor by employing Low Frequency Current Balancing (LFCB) technique. The chip is implemented in 0.18μm CMOS process achieving 86.55% peak efficiency while tracking a 10MHz LTE envelope signal.