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Dive into the research topics where Se-Won Wang is active.

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Featured researches published by Se-Won Wang.


international solid-state circuits conference | 2007

A Single-Inductor Switching DC–DC Converter With Five Outputs and Ordered Power-Distributive Control

Hanh-Phuc Le; Chang-Seok Chae; Kwang-Chan Lee; Gyu-Hyeong Cho; Se-Won Wang; Gyu-Ha Cho; Sung-il Kim

An integrated 5-output single-inductor multiple-output DC-DC converter with ordered power-distributive control in a 0.5mum BiCMOS process is presented. The converter has four main positive boost outputs programmable from +5 to +12V and one dependent negative output from -12 to -5V. A maximum efficiency of 80.8% is achieved at a total output power of 450mW, with a switching frequency of 700kHz.


international solid-state circuits conference | 2012

A 40 mV Transformer-Reuse Self-Startup Boost Converter With MPPT Control for Thermoelectric Energy Harvesting

Jong-Pil Im; Se-Won Wang; Kang-Ho Lee; Young-Jin Woo; Young-Sub Yuk; Tae-Hwang Kong; Sung-Wan Hong; Seung-Tak Ryu; Gyu-Hyeong Cho

This paper presents transformer-based self-starting boost converter architecture with low-power maximum power point tracking (MPPT) control for low-voltage thermoelectric generator applications. The minimum working voltage of the proposed boost converter is 40 mV with oscillation through a positive feedback loop formed by a native MOS and transformer. The oscillation autonomously starts up by thermal noise and VOUT is charged up to 1.2 V by the oscillation so that the control block can operate. After that, the transformer for start-up is reused as an inductor, and the normal boost converter mode is enabled for better energy transfer efficiency. An improved MPPT sensing method is also proposed to simplify the circuit. The prototype chip is implemented in a 0.13-μm CMOS process. It operates with an input voltage range of 40 mV to 300 mV and provides a maximum output power of 2.7 mW with a maximum efficiency of 61% at an output voltage of 2 V.


international solid-state circuits conference | 2012

A high-stability emulated absolute current hysteretic control single-inductor 5-output switching DC-DC converter with energy sharing and balancing

Se-Won Wang; Gyu-Ha Cho; Gyu-Hyeong Cho

Several types of DC-DC converters for active-matrix organic LED (AMOLED) displays have been introduced to date [1-4]. Single-inductor multiple-output (SIMO) converters with current-mode control have many advantages including reduced PCB space and less cost for mass-production due to the use of only one off-chip inductor to provide many outputs [1,2]. However, a load-dependent stability issue has to be addressed which is due to the output capacitance and an internal integrator with an error amplifier. Recently, in efforts to overcome the stability issue of current-mode control, load-independent control converters have been developed. Although this concept works well, the inductor-current sensing and artificial ramp generation for stability still make the controller complicated [3,4]. In addition, the freewheeling current control converter requires an extra power switch for freewheeling current flow, thereby lowering power efficiency [3]. The vestigial current control converter, meanwhile, has weak points of requiring auxiliary output and an additional inductor, and thus consumes some additional power in the steady state [4]. Besides the controller issue, the previous converters when operating with a large step-up ratio, usually have heavy voltage stress applied to the inductor, resulting in a low efficiency [1,4]. To overcome these problems, the proposed SIMO converter employs emulated absolute current hysteretic control, which uses full current information and is characterized by intrinsic high stability. The energy sharing capacitor is also used for high output voltage to reduce the voltage swing of the switching node and the associated loss. In addition, to balance the total energy across the inductor, the energy balancing capacitor is adopted.


international solid-state circuits conference | 2011

Zero-order control of boost DC-DC converter with transient enhancement using residual current

Tae-Hwang Kong; Young-Jin Woo; Se-Won Wang; Sung-Wan Hong; Gyu-Hyeong Cho

A variety of controllers are used in DC-DC converters. Among them, voltage-mode control and current-programmed-mode control are widely used in industrial applications. In such controllers, however, values of inductor, output capacitor, and/or load condition usually affect loop stability and limit the performance of switching converter. Recently, load-independent-control (LIC) method is reported, where freewheeling current is fed back to overcome such a limitation [1]. While this is a viable solution in principle, it still has a vulnerable aspect that must be addressed: the feedback control is affected by the level of freewheeling current and an extra power switch is needed for freewheeling current flow which lowers power efficiency. Another LIC method using vestigial current control is reported in [2]. The weak points of vestigial control are that it needs an auxiliary output and power is consumed in steady state to regulate vestigial current. In this paper, we present a zero-order-controlled (ZOC) boost DC-DC converter that has a robust control loop and does not consume any extra power in the steady state.


symposium on vlsi circuits | 2012

High area-efficient DC-DC converter using Time-Mode Miller Compensation (TMMC)

Sung-Wan Hong; Tae-Hwang Kong; Seungchul Jung; Sungwoo Lee; Se-Won Wang; Jong-Pil Im; Gyu-Hyeong Cho

For the controller design of a DC-DC converter, a Time-Mode Miller Compensation (TMMC) is introduced in this paper. Using this concept, the consuming area of the DC-DC converter can be significantly reduced without any off-chip compensation components. The chip is implemented in 0.18μm I/O CMOS whose size is similar to 0.35μm CMOS, and the core size of this work is only 0.12mm2. Peak efficiency is 90.6%, with switching frequency of 1.15MHz.


european solid-state circuits conference | 2012

A CMOS LDO regulator with high PSR using Gain Boost-Up and Differential Feed Forward Noise Cancellation in 65nm process

Young-Sub Yuk; Seungchul Jung; Byunghun Lee; Se-Won Wang; Chul Kim; Gyu-Hyeong Cho

A 65nm CMOS Low Drop-Out (LDO) Regulator is presented employing Gain Boost-Up and Differential Feed Forward Noise Cancellation (DFFNC) to maximize the Power Supply Rejection. The gain boost-up consists of both negative feedback and positive feedback in the error amplifier. With a 1.2V supply voltage, this LDO regulator has a 200mV drop-out voltage and the ability to handle a maximum 25mA load current. The measurement results show a -47dB PSR ratio up to 10MHz and 0.8% of load regulation for the full load current change.


international conference of the ieee engineering in medicine and biology society | 2010

An electronic DNA sensor chip using integrated capacitive read-out circuit

Byunghun Lee; Kang-Ho Lee; Jeong-Oen Lee; Mi-Jin Sohn; Sukhwan Choi; Se-Won Wang; Jun-Bo Yoon; Gyu-Hyeong Cho

This paper presents fully integrated label-free DNA recognition circuit based on capacitance measurement. A CMOS-based DNA sensor is implemented for the electrical detection of DNA hybridization. The proposed architecture detects the difference of capacitance through the integration of current mismatch of capacitance between reference electrodes functionalized with only single-stranded DNA and sensing electrodes bound with complementary DNA strands specifically. In addition, to minimize the effects of parallel resistance between electrodes and DNA layers, the compensation technique of leakage current through the use of constant current charging and discharging is implemented in the proposed detection circuit. The chip was fabricated in 0.35um 4-metal 2-poly CMOS process, and 16×8 sensing electrode arrays were fabricated by post-processing steps.


IEEE Journal of Solid-state Circuits | 2013

Zero

Tae-Hwang Kong; Young-Jin Woo; Se-Won Wang; Yong-Joon Jeon; Sung-Wan Hong; Gyu-Hyeong Cho

This paper proposes a new control scheme of zeroth-order control (ZOC) for PWM DC-DC converters in which the pole frequencies of the control loop are no longer dependent on the values of the inductor, output capacitor, or the output load current. In the proposed scheme, the output voltage of the converter is regulated by a comparator. The main control loop of the converter regulates the inductor energy which is built up to an optimum value to be delivered to the output by means of the time interval between the rising edge of the main switch driving pulse and the comparator output pulse. A boost DC-DC converter with the proposed ZOC has been implemented and fabricated in a commercial 0.35 μm BCDMOS process. A maximum efficiency of 88% is achieved at a total output power of 480 mW with the switching frequency of 833 kHz when the input voltage and the output voltage are 3.7 V and 8 V, respectively. Over 85% efficiency is maintained for a wide range of the output load current from 40 mA to 300 mA.


applied power electronics conference | 2011

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Se-Won Wang; Young-Jin Woo; Young-Sub Yuk; Byunghun Lee; Gyu-Ha Cho; Gyu-Hyeong Cho

20V maximum input voltage and 1A load current hysteretic control based monolithic buck converter with phase locked loop (PLL) is presented. To achieve advantage of hysteretic control and reduce inductor current ripple with ceramic output capacitor, hysteretic based control with PLL is adopted. Furthermore, in order to decrease inductor current ripple due to wide input voltage range, switching frequency is adapted to the input supply voltage. This buck converter is fabricated with 0.35 μm high voltage BiCMOS-DMOS (BCD) process.


symposium on vlsi circuits | 2010

-Order Control of Boost DC-DC Converter With Transient Enhancement Scheme

Se-Won Wang; Young-Jin Woo; Young-Sub Yuk; Gyu-Hyeong Cho; Gyu-Ha Cho

A hybrid-type Single Inductor Boost/Buck Inverting Flyback(SIBBIF) DC-DC Converter is presented. To increase the converter efficiency, a flying capacitor as well as an inductor is adopted as another energy transfer medium together with multi-level gate driver (MLGD). Besides, to enhance load transient response, hybrid fast transient control (HFTC) is adopted. The proposed chip is implemented in a 0.5-µm power BCD process and operates at 1.25 MHz with a max efficiency of 87.1% at an output power of 600 mW.

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