Tae-Hwang Kong

A 40 mV Transformer-Reuse Self-Startup Boost Converter With MPPT Control for Thermoelectric Energy Harvesting

This paper presents transformer-based self-starting boost converter architecture with low-power maximum power point tracking (MPPT) control for low-voltage thermoelectric generator applications. The minimum working voltage of the proposed boost converter is 40 mV with oscillation through a positive feedback loop formed by a native MOS and transformer. The oscillation autonomously starts up by thermal noise and VOUT is charged up to 1.2 V by the oscillation so that the control block can operate. After that, the transformer for start-up is reused as an inductor, and the normal boost converter mode is enabled for better energy transfer efficiency. An improved MPPT sensing method is also proposed to simplify the circuit. The prototype chip is implemented in a 0.13-μm CMOS process. It operates with an input voltage range of 40 mV to 300 mV and provides a maximum output power of 2.7 mW with a maximum efficiency of 61% at an output voltage of 2 V.

Zero-order control of boost DC-DC converter with transient enhancement using residual current

A variety of controllers are used in DC-DC converters. Among them, voltage-mode control and current-programmed-mode control are widely used in industrial applications. In such controllers, however, values of inductor, output capacitor, and/or load condition usually affect loop stability and limit the performance of switching converter. Recently, load-independent-control (LIC) method is reported, where freewheeling current is fed back to overcome such a limitation [1]. While this is a viable solution in principle, it still has a vulnerable aspect that must be addressed: the feedback control is affected by the level of freewheeling current and an extra power switch is needed for freewheeling current flow which lowers power efficiency. Another LIC method using vestigial current control is reported in [2]. The weak points of vestigial control are that it needs an auxiliary output and power is consumed in steady state to regulate vestigial current. In this paper, we present a zero-order-controlled (ZOC) boost DC-DC converter that has a robust control loop and does not consume any extra power in the steady state.

High Area-Efficient DC-DC Converter With High Reliability Using Time-Mode Miller Compensation (TMMC)

This paper presents a novel on-chip compensation scheme, the Time-Mode Miller Compensation (TMMC), for DC-DC converter in which the compensation components are integrated on-chip. Using this proposed scheme, the DC-DC converter is stably compensated and insensitive to process variations, with significantly small compensation components ( 1 pF and 80 kΩ in this work) consuming very small silicon area owing to the characteristic of the TMMC. The small compensation components make the chip size small, with 0.12 mm2 of core area (w/o power transistors) using 0.18 μm I/O process. This core size is as small as that of the digital DC-DC converters implemented with less than sub-50 nm process. The measurement result shows that the maximum power efficiency of 90.6% is obtained at the load current of 220 mA with the switching frequency of 1.15 MHz when the input and the output voltages are 3.3 V and 2 V, respectively.

High area-efficient DC-DC converter using Time-Mode Miller Compensation (TMMC)

For the controller design of a DC-DC converter, a Time-Mode Miller Compensation (TMMC) is introduced in this paper. Using this concept, the consuming area of the DC-DC converter can be significantly reduced without any off-chip compensation components. The chip is implemented in 0.18μm I/O CMOS whose size is similar to 0.35μm CMOS, and the core size of this work is only 0.12mm2. Peak efficiency is 90.6%, with switching frequency of 1.15MHz.

Zero

This paper proposes a new control scheme of zeroth-order control (ZOC) for PWM DC-DC converters in which the pole frequencies of the control loop are no longer dependent on the values of the inductor, output capacitor, or the output load current. In the proposed scheme, the output voltage of the converter is regulated by a comparator. The main control loop of the converter regulates the inductor energy which is built up to an optimum value to be delivered to the output by means of the time interval between the rising edge of the main switch driving pulse and the comparator output pulse. A boost DC-DC converter with the proposed ZOC has been implemented and fabricated in a commercial 0.35 μm BCDMOS process. A maximum efficiency of 88% is achieved at a total output power of 480 mW with the switching frequency of 833 kHz when the input voltage and the output voltage are 3.7 V and 8 V, respectively. Over 85% efficiency is maintained for a wide range of the output load current from 40 mA to 300 mA.

^{\rm th}

Herein we propose a new PWM controller for a DC-DC converter with a Self-aligned Comparator Control (SCC), the purpose of which is to overcome sub-harmonic switching and hysteretic characteristics that are problematic in conventional comparator control schemes. In the proposed scheme, the condition of the output voltage is converted to the form of a phase difference through the SCC block. The main control loop of the converter regulates the inductor current which is built up to an optimum value by using this phase difference. In addition to the SCC, the proposed PWM controller is fully integrated on-chip without off-chip components to decrease the size and cost of the DC-DC converter using a new Switching Noise Robust Charge-pump (SNRC). A boost DC-DC converter with the proposed SCC and SNRC was designed and fabricated in a commercial 0.35 μm BCDMOS process with total controller area of 0.791 mm2 . A maximum efficiency of 90% was achieved at a total output power of 480 mW with a switching frequency of 926 kHz when the input and the output voltages were 3.7 V and 8 V, respectively. Over 85% efficiency was maintained over a wide range of output load current from 40 mA to 300 mA.

-Order Control of Boost DC-DC Converter With Transient Enhancement Scheme

A DC-DC converter, which tracks minimum power loss under various conditions, is presented in this paper. With this DC-DC converter, a new approach for optimum efficiency, which implements theoretical equations intactly at the circuit level, was adopted. This approach has high reliability against process variation. The concept of lossless soft-switching was also adopted in discontinuous-conduction-mode (DCM) operation. The proposed DC-DC converter has a maximum power efficiency of 91% at the switching frequency of 1 MHz. The proposed converter is able to maintain a maximum power efficiency of around 90% over the whole range of input voltage from 2.9 to 4.5 V and output voltage from -3.8 to -5.9 V. This chip is implemented in a 0.35 μm BCD process and occupies an area of 2.1 ×1.4 mm2.

A 0.791 mm

A new Ripple Current Controlled Boost Converter with capacitor-free LDO as a power IC for digital driving AMOLED display is presented to achieve high stability for load variation. And a flying capacitor as well as an inductor is adopted as another energy transfer medium to increase the converter efficiency. The proposed chip is implemented in a 0.35-μm power BCD process. Transient dip voltage of the proposed boost converter is 30mV with 70mA load change. A peak efficiency of 90% at an output power of 480mW is measured without LDOs. The maximum power is 1.5W.

^{2}

The luminance of AMOLED displays varies depending on the temperature owing to panel degradation. In this paper, a luminance compensation method using a monitor pixel with a multiple output boost converter and DAC for digital driving scheme is introduced. This method makes the panel luminance constant irrespective of the temperature. Furthermore, it has lower power consumption compared with the previous compensation method using monitor pixel.

On-Chip Self-Aligned Comparator Controller for Boost DC-DC Converter Using Switching Noise Robust Charge-Pump

A pulse-width-modulation light emission diode (LED) current driver for Back Light Unit in mobile liquid crystal display with minimum operable drain voltage of 360mV and 3σ current accuracy of 3% without trimming is proposed in 0.35μm BCD process. S/H type structure with sequential channel driving scheme reduces power consumption as reference current of current mirror with accurate output current. High reference current is just applied for the enhanced matching in sampling phase, while reference current is minimized in holding phase. The proposed triggered buffer amplifier enables fast and accurate PWM current driving.