Sunghoon Chun

MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs

Unacceptable loss of signal integrity may cause permanent or intermittent harm to the functionality and performance of SoCs. In this paper, we present an abstract model and a new test pattern generation method of signal integrity problems on interconnects. This approach is achieved by considering the effects for testing inputs and parasitic RLC elements of interconnects. We also develop a framework to deal with arbitrary interconnection topology. Experimental results show that the proposed signal integrity fault model is more exact and more powerful for long interconnects than previous approaches.

An Effective Hybrid Test Data Compression Method Using Scan Chain Compaction and Dictionary-Based Scheme

In this paper, we propose a new test data compression method for reducing test data volume and test application time. The proposed method consists of two steps: scan chain compaction and dictionary-based compression scheme. The scan chain compaction provides a minimum scan chain depth by using compaction of the compatible scan cells in the scan chain. The compacted scan chain is partitioned to the multiple internal scan chains for using the fixed-length index dictionary-based compression scheme that provides the high compression ratio and the fast testing time. The proposed compression method delivers compressed patterns from the ATE to the chip and drives a large number of multiple internal scan chains using only a single ATE input and output. Experimental results for the ISCAS-89 test benches show that the test data volume and testing time for the proposed method are less than previous compression schemes.

An Efficient Scan Chain Diagnosis Method Using a New Symbolic Simulation

Locating the scan chain faults is very important for dedicated IC manufacturers to guide the failure analysis process for yield improvement. In this paper, we propose a new symbolic simulation based scan chain diagnosis method to solve the scan chain diagnosis resolution problem as well as the multiple faults problem. The proposed method uses a new symbolic simulation with the faulty probabilities of a set of candidate faulty scan cells in a bounded range and to analyze the effects caused by faulty scan cells in good scan chains. In addition, we use the faulty information in good scan chains that are not contaminated by the faults while unloading scan out responses. In addition, a new score matching method is proposed to effectively handle multiple faults and to improve the diagnostic resolution by ranking the candidate scan cells in the candidate list. Experimental results demonstrate the effectiveness of the proposed method.

An Effective Power Reduction Methodology for Deterministic BIST Using Auxiliary LFSR

Power consumption for test vectors is a major problem in SOC testing using BIST. A new low power testing methodology to reduce the peak power and average power associated with scan-based designs in the deterministic BIST is proposed. This new method utilizes an auxiliary LFSR to reduce the amount of the switching activity in the deterministic BIST. Excessive transition detector (ETD) monitors the number of transitions in the test pattern generated by LFSR and the low transition pattern is generated for excessive transition region using an auxiliary LFSR. Experimental results for the larger ISCAS 89 benchmarks show that reduced peak power and average power can indeed be achieved with little hardware overhead compared to previous schemes.

High-MDSI: A High-level Signal Integrity Fault Test Pattern Generation Method for Interconnects

Unacceptable loss of signal integrity may cause permanent or intermittent harm to the functionality and performance of SoCs. In this paper, considering the interconnection topology information, an abstract model and a new test pattern generation method of signal integrity problems on interconnects are proposed. In addition, previous SPICE- based pattern generation methods are too complex and time consuming to generate test patterns for signal integrity faults. To overcome this problem, we also develop a new high-level test pattern generation method by using the abstract signal integrity fault model. Experimental results show that the proposed signal integrity fault model is more exact for long interconnects than previous approaches. In addition, the proposed method is much faster than the SPICE-based pattern generation method.

A New Scan Chain Fault Simulation for Scan Chain Diagnosis

In this paper, we propose a new symbolic simulation for scan chain diagnosis to solve the diagnosis resolution problem. The proposed scan chain fault simulation, called the SF-simulation, is able to analyze the effects caused by faulty scan cells in good scan chains. A new scan chain fault simulation is performed with a modified logic ATPG pattern. In this simulation, we consider the effect of errors caused by scan shifting in the faulty scan chain. Therefore, for scan chain diagnosis, we use the faulty information in good scan chains which are not contaminated by the faults while unloading scan out responses. The SF-simulation can tighten the size of the candidate list and achieve a high diagnosis resolution by analyzing fault effects of good scan chains, which are ignored by most previous works. Experimental results demonstrate the effectiveness of the proposed method.

A High-Level Signal Integrity Fault Model and Test Methodology for Long On-Chip Interconnections

In this paper, considering the interconnection topology information, an abstract model and a new test pattern generation method of signal integrity problems on interconnects are proposed. In addition, previous SPICE-based pattern generation methods are too complex and time consuming to generate test patterns for signal integrity faults. To more accurately detect signal integrity defects on practical on-chip interconnection lines and avoid time consuming for interconnection analysis, in this paper, we propose a new high-level signal integrity fault model to estimate noise effects based on process variation and interconnect signal transition. Experimental results show that the proposed signal integrity fault model is more exact for long interconnects than previous approaches. In addition, the proposed method is much faster than the SPICE-based pattern generation method.

A New Wafer Level Latent Defect Screening Methodology for Highly Reliable DRAM Using a Response Surface Method

Screening latent defects in a wafer test process is very important task in both reducing memory manufacturing cost and enhancing the reliability of emerging package products such as SIP, MCP, and WSP. In terms of the package assembly cost, these package products are required to adopt the KGD (known good die) quality level. However, the KGD requires a long burn-in time, added testing time, and high cost equipments. To alleviate these problems, this paper presents a statistical wafer burn-in methodology for the latent defect screen in the wafer test process. The newly proposed methodology consists of a defect-based wafer burn-in (DB-WBI) stress method based on DRAM operation characteristics and a statistical stress optimization method using RSM (response surface method) on the DRAM manufacturing test process. Experimental data shows that package test yields in the immature fabrication process improved by up to 6%. In addition, experimental results show that the proposed methodology can guarantee reliability requirements with a shortened package burn-in time. In conclusion, this methodology realizes a simplified manufacturing test process supporting time to market with high reliability.

XPDF-ATPG: An Efficient Test Pattern Generation for Crosstalk-Induced Faults

In this paper, we propose a new test generation method for delay faults considering crosstalk-induced delay effects, based on a conventional delay ATPG technique in order to reduce the complexity of previous ATPG algorithm for crosstalk delay faults and to consider multiple aggressor crosstalk faults to maximize the noise of the victim line. Since the proposed ATPG for crosstalk-induced delay faults uses the physical and timing information, the proposed ATPG can reduce the search space of the backward implication of the aggressors constraints and it is helpful for reducing the time cost of the ATPG than previous works. In addition, since the proposed technique targets on the critical path for the original delay test as the victim lines, it can improve test effectiveness of delay testing. Experimental results demonstrate the effectiveness of the proposed method.

An Efficient Dictionary Organization for Maximum Diagnosis

The major problem of fault diagnosis with a fault dictionary is the enormous amount of data. The technique used to manage this data can have a significant effect on the outcome of the fault diagnosis procedure. If information is removed from a fault dictionary in order to reduce the size of the dictionary, its ability to diagnose stuck-at faults and unmodeled faults may be severely debased. Therefore, we focus on methods for producing a dictionary that is both small and lossless-compacted.We propose an efficient dictionary for maximum diagnosis, which is called SD-Dictionary. This dictionary consists of a static sub-dictionary and a dynamic sub-dictionary in order to make a smaller dictionary while maintaining the critical information needed for the diagnostic ability. Experimental results on ISCAS’ 85, ISCAS’ 89 and ITC’ 99 benchmark circuits show that the size of the proposed dictionary is substantially reduced, while the dictionary retains most or all of the diagnostic capability of the full dictionary.