Yongjoon Kim

Interleukin-1β induced by Helicobacter pylori infection enhances mouse gastric carcinogenesis.

Interleukin-1β (Il1b) is considered to be involved in Helicobacter pylori (HP)-induced human gastric carcinogenesis, while the role of its polymorphisms in gastric cancer susceptibility remains controversial. Here, we aimed to clarify the role of HP infection-induced IL1B in gastric inflammation and carcinogenesis using Il1b(-/-) (Il1b-null) mice. In gastric mucosa of the Il1b(+/+) (WT) mice, HP infection induced Il1b expression and severe inflammation. In contrast, in Il1b-null mice, recruitment of neutrophils and macrophages by HP infection was markedly suppressed. In a carcinogenicity test, the multiplicity of gastric tumors was significantly suppressed in theIl1b-null mice (58% of WT; P<0.005). Mechanistically, HP infection induced NF-κB activation both in the inflammatory and epithelial cells in gastric mucosae, and the activation was attenuated in the Il1b-null mice. Accordingly, increased proliferation and decreased apoptosis of gastric epithelial cells induced by HP infection in the WT mice were attenuated in the Il1b-null mice. These results demonstrated that the IL1B physiologically induced by HP infection enhanced gastric carcinogenesis by affecting both inflammatory and epithelial cells.

Segmented scan architecture using segment grouping for test cost reduction

This paper presents a segmented scan architecture to reduce both test application time and test power consumption. The proposed scan architecture partitions scan chains into several segments and groups these segments into several compatible segment groups. All segments within each compatible segment group are filled with test vector data in parallel. Since scan shift operations are limited to segments, the test application time and test power can be significantly reduced.

MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs

Unacceptable loss of signal integrity may cause permanent or intermittent harm to the functionality and performance of SoCs. In this paper, we present an abstract model and a new test pattern generation method of signal integrity problems on interconnects. This approach is achieved by considering the effects for testing inputs and parasitic RLC elements of interconnects. We also develop a framework to deal with arbitrary interconnection topology. Experimental results show that the proposed signal integrity fault model is more exact and more powerful for long interconnects than previous approaches.

A new maximal diagnosis algorithm for interconnect test

Interconnect test for highly integrated environments becomes more important in terms of its test time and a complete diagnosis, as the complexity of the circuit increases. Since the board-level interconnect test is based on boundary scan technology, it takes a long test time to apply test vectors serially through a long scan chain. Complete diagnosis is another important issue. Since the board-level test is performed for repair, noticing the faulty position is an essential element of any interconnect test. Generally, the interconnect test algorithms that need a short test time cannot perform the complete diagnosis and the algorithms that perform the complete diagnosis need a lengthy test time. To overcome this problem, a new interconnect test algorithm is developed. The new algorithm can provide the complete diagnosis of all faults with a shorter test time compared to the previous algorithms.

An Effective Hybrid Test Data Compression Method Using Scan Chain Compaction and Dictionary-Based Scheme

In this paper, we propose a new test data compression method for reducing test data volume and test application time. The proposed method consists of two steps: scan chain compaction and dictionary-based compression scheme. The scan chain compaction provides a minimum scan chain depth by using compaction of the compatible scan cells in the scan chain. The compacted scan chain is partitioned to the multiple internal scan chains for using the fixed-length index dictionary-based compression scheme that provides the high compression ratio and the fast testing time. The proposed compression method delivers compressed patterns from the ATE to the chip and drives a large number of multiple internal scan chains using only a single ATE input and output. Experimental results for the ISCAS-89 test benches show that the test data volume and testing time for the proposed method are less than previous compression schemes.

An Efficient Scan Chain Diagnosis Method Using a New Symbolic Simulation

Locating the scan chain faults is very important for dedicated IC manufacturers to guide the failure analysis process for yield improvement. In this paper, we propose a new symbolic simulation based scan chain diagnosis method to solve the scan chain diagnosis resolution problem as well as the multiple faults problem. The proposed method uses a new symbolic simulation with the faulty probabilities of a set of candidate faulty scan cells in a bounded range and to analyze the effects caused by faulty scan cells in good scan chains. In addition, we use the faulty information in good scan chains that are not contaminated by the faults while unloading scan out responses. In addition, a new score matching method is proposed to effectively handle multiple faults and to improve the diagnostic resolution by ranking the candidate scan cells in the candidate list. Experimental results demonstrate the effectiveness of the proposed method.

An Effective Power Reduction Methodology for Deterministic BIST Using Auxiliary LFSR

Power consumption for test vectors is a major problem in SOC testing using BIST. A new low power testing methodology to reduce the peak power and average power associated with scan-based designs in the deterministic BIST is proposed. This new method utilizes an auxiliary LFSR to reduce the amount of the switching activity in the deterministic BIST. Excessive transition detector (ETD) monitors the number of transitions in the test pattern generated by LFSR and the low transition pattern is generated for excessive transition region using an auxiliary LFSR. Experimental results for the larger ISCAS 89 benchmarks show that reduced peak power and average power can indeed be achieved with little hardware overhead compared to previous schemes.

High-MDSI: A High-level Signal Integrity Fault Test Pattern Generation Method for Interconnects

Unacceptable loss of signal integrity may cause permanent or intermittent harm to the functionality and performance of SoCs. In this paper, considering the interconnection topology information, an abstract model and a new test pattern generation method of signal integrity problems on interconnects are proposed. In addition, previous SPICE- based pattern generation methods are too complex and time consuming to generate test patterns for signal integrity faults. To overcome this problem, we also develop a new high-level test pattern generation method by using the abstract signal integrity fault model. Experimental results show that the proposed signal integrity fault model is more exact for long interconnects than previous approaches. In addition, the proposed method is much faster than the SPICE-based pattern generation method.

An Effective Test Pattern Generation for Testing Signal Integrity

As more cores are integrated in a single chip with sophisticated process like nanotechnology, testing signal integrity between the cores needs much effort due to complicate coupling effects. In this paper, we propose a novel test pattern generation method for testing signal integrity. Using this method, short and effective test patterns are generated with low hardware overhead. It can be used for self-test scheme and experimental results show the effectiveness of the proposed scheme

A High-Level Signal Integrity Fault Model and Test Methodology for Long On-Chip Interconnections

In this paper, considering the interconnection topology information, an abstract model and a new test pattern generation method of signal integrity problems on interconnects are proposed. In addition, previous SPICE-based pattern generation methods are too complex and time consuming to generate test patterns for signal integrity faults. To more accurately detect signal integrity defects on practical on-chip interconnection lines and avoid time consuming for interconnection analysis, in this paper, we propose a new high-level signal integrity fault model to estimate noise effects based on process variation and interconnect signal transition. Experimental results show that the proposed signal integrity fault model is more exact for long interconnects than previous approaches. In addition, the proposed method is much faster than the SPICE-based pattern generation method.