Myung-Hoon Yang

Segmented scan architecture using segment grouping for test cost reduction

This paper presents a segmented scan architecture to reduce both test application time and test power consumption. The proposed scan architecture partitions scan chains into several segments and groups these segments into several compatible segment groups. All segments within each compatible segment group are filled with test vector data in parallel. Since scan shift operations are limited to segments, the test application time and test power can be significantly reduced.

A New Low Power Test Pattern Generator using a Transition Monitoring Window based on BIST Architecture

This paper presents a new low power BIST TPG scheme. It uses a transition monitoring window (TMW) that is comprised of a transition monitoring window block and a MUX. When random test patterns are generated by an LFSR, transitions of those patterns satisfy pseudo-random Gaussian distribution. The proposed technique represses transitions of patterns using the k-value which is a standard that is obtained from the distribution of TMW to observe over transitive patterns causing high power dissipation in a scan chain. Experimental results show that the proposed BIST TPG schemes can reduce scan transition by about 60% without performance loss in ISCAS’89 benchmark circuits that have large number scan inputs.

An Effective Hybrid Test Data Compression Method Using Scan Chain Compaction and Dictionary-Based Scheme

In this paper, we propose a new test data compression method for reducing test data volume and test application time. The proposed method consists of two steps: scan chain compaction and dictionary-based compression scheme. The scan chain compaction provides a minimum scan chain depth by using compaction of the compatible scan cells in the scan chain. The compacted scan chain is partitioned to the multiple internal scan chains for using the fixed-length index dictionary-based compression scheme that provides the high compression ratio and the fast testing time. The proposed compression method delivers compressed patterns from the ATE to the chip and drives a large number of multiple internal scan chains using only a single ATE input and output. Experimental results for the ISCAS-89 test benches show that the test data volume and testing time for the proposed method are less than previous compression schemes.

An efficient pipelined parallel architecture for blocking effect removal in HDTV

This paper presents an efficient architecture for blocking effect removal in HDTV. Since there is a large amount of image signal for processing in digital HDTV, the memory size and fast operation have been the main concerns of the DSP (digital signal processing) architectures. To reduce the size of the memory, the memory is partitioned into many memory banks. This makes it possible to access the memory concurrently. Also, to improve the operation speed, a pipelined parallel architecture and a memory scheduling technique are adopted. Since multiplications and divisions are time-critical, these operations are replaced with shiftings. Therefore this architecture is very fast and uses small size memory banks, and this makes it possible to realize a real-time signal processor.

An Effective Power Reduction Methodology for Deterministic BIST Using Auxiliary LFSR

Power consumption for test vectors is a major problem in SOC testing using BIST. A new low power testing methodology to reduce the peak power and average power associated with scan-based designs in the deterministic BIST is proposed. This new method utilizes an auxiliary LFSR to reduce the amount of the switching activity in the deterministic BIST. Excessive transition detector (ETD) monitors the number of transitions in the test pattern generated by LFSR and the low transition pattern is generated for excessive transition region using an auxiliary LFSR. Experimental results for the larger ISCAS 89 benchmarks show that reduced peak power and average power can indeed be achieved with little hardware overhead compared to previous schemes.

An Effective Test Pattern Generation for Testing Signal Integrity

As more cores are integrated in a single chip with sophisticated process like nanotechnology, testing signal integrity between the cores needs much effort due to complicate coupling effects. In this paper, we propose a novel test pattern generation method for testing signal integrity. Using this method, short and effective test patterns are generated with low hardware overhead. It can be used for self-test scheme and experimental results show the effectiveness of the proposed scheme

An effective parallel ALPG using instruction unrolling for high speed memory testing

This paper presents the design and implementation of a new parallel Algorithmic Pattern Generator (ALPG) of Automatic Test Equipment (ATE) for the high speed memory testing. We implemented the Instruction Analyzer (IA) that unrolls the instructions using simple instructions. And, unrolled instruction memory is also implemented to reduce the delay of the IA. These implementations allow the ALPG to operate flexible algorithms at high speed. For high speed, we also designed the ALPG of multiple Pattern Generators (PG) with phase-shifting clocks. Therefore, the ALPG has expandability and operates at high speed with the high flexibility of the algorithms.

XPDF-ATPG: An Efficient Test Pattern Generation for Crosstalk-Induced Faults

In this paper, we propose a new test generation method for delay faults considering crosstalk-induced delay effects, based on a conventional delay ATPG technique in order to reduce the complexity of previous ATPG algorithm for crosstalk delay faults and to consider multiple aggressor crosstalk faults to maximize the noise of the victim line. Since the proposed ATPG for crosstalk-induced delay faults uses the physical and timing information, the proposed ATPG can reduce the search space of the backward implication of the aggressors constraints and it is helpful for reducing the time cost of the ATPG than previous works. In addition, since the proposed technique targets on the critical path for the original delay test as the victim lines, it can improve test effectiveness of delay testing. Experimental results demonstrate the effectiveness of the proposed method.