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Dive into the research topics where Sunil Sudhakaran is active.

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Featured researches published by Sunil Sudhakaran.


international symposium on electromagnetic compatibility | 2013

Study of BGA package cap for high-performance computing GPU

Wenjie Mao; Yaping Zhou; Aniket Naik; Sunil Sudhakaran

GPU for high performance computing shows high current consumption and fast current variation which presents a big design challenge for power delivery. In this paper, power delivery design for a computing GPU is discussed focusing on package capacitors. Current behaviour of a computing application is illustrated first. The related power delivery challenge is presented with simulation and measurement. Next package capacitors are proposed to reduce noise and studied via simulation according to their placement, value, number, and type. Simulation data shows land side cap placed between IO rails and core VDD balls can effectively reduce power delivery noise without compromising BGA density. Measurement data correlates well with simulated power noise. There is about a 55mv noise improvement which yields a gain of 150MHz in GPU operational frequency.


electrical performance of electronic packaging | 2016

Power delivery network design and modeling for High Bandwidth Memory (HBM)

Wenjun Shi; Yaping Zhou; Sunil Sudhakaran

A modeling method to consider simulation switching noise of HBM and its impact on HBM timing is described. This method combines partial element equivalent circuit model for power delivery network and S-parameters based HBM channel model together in HBM studies.


electrical performance of electronic packaging | 2014

Modeling and measurement of noise aware clocking in power supply noise analysis

Yaping Zhou; Sunil Sudhakaran; Aniket Naik; Xin Chang; Daniel Lin; Tezaswi Raja; Sachin Idgunji

Power noise aware clocking in modern chips can reduce power supply noises and relax on-chip timing requirements during power drooping. This paper proposes and demonstrates a power noise simulation method to consider these two effects. Measurement results are also presented.


electrical performance of electronic packaging | 2016

8B9B encoding for crosstalk reduction in a high-speed parallel bus

Sunil Sudhakaran; Russell R. Newcomb

This paper presents a new encoding and corresponding decoding scheme to reduce crosstalk on a high-speed parallel bus. The scheme is based on a modified Fibonacci sequence and is introduced along with potential benefits in some upcoming memory interfaces. The scheme provides appreciable eye opening for interfaces dominated by crosstalk such as existing memory interfaces.


electrical performance of electronic packaging | 2016

Reflection de-embedding for high-speed I/O measurements

Sunil Sudhakaran; Daniel Lin

Reflections in high-speed busses can corrupt signal measurements when the probe location is away from the DUT. This paper presents a methodology to remove such reflections. A mathematical formulation of the problem is presented along with solutions to commonly encountered topologies.


ieee antennas and propagation society international symposium | 2014

Efficient electromagnetic modeling and analysis for off-chip interconnects in SIW structures and 3D ICs

Xin Chang; Leung Tsang; Sunil Sudhakaran

In this work, we use a mostly analytical approach of Foldy-Lax multiple scattering equation method to efficiently model and solve physical/electromagnetics properties of the structures of SIW based devices and 3D IC in chip-package-board system which include multiple vertical and horizontal interconnects. We decompose the modes effects inside the target structures into modes of cavity with multiple vertical interconnects and modes of horizontal interconnects which are traces. The coupling among vertical interconnects are solved by applying Foldy-Lax multiple scattering equation. The waveguide and cavity modes are decoupled in the Foldy-Lax equations. The modes effects of vertical interconnects and horizontal interconnects are finally integrated together to obtain the scattering matrix of off-chip interconnects. Numerical results for the method are in good agreement with a commercial full wave numerical tool up to 40 GHz.


electronic components and technology conference | 2013

Simultaneous switching noise model by distributed power port and ground current capture

Seunghyun Hwang; Daehyun Chung; Venkat Satagopan; Sunil Sudhakaran; Dongyang Lin; Fathi Moghadam

In this paper, distributed power port method for the loop-inductance based simulation is proposed to take into account local impedance variations of the complex power plane in high-speed printed circuit boards and packages. Lumped power port method is not appropriate to model distributed power supply noise across multiple bytes whereas distributed power port can be used for byte-level granularity noise analysis as well as capturing transfer-impedance effect. In time-domain analysis, a new method to capture ground current is developed to compensate the drawback of the loop-inductance based simulation tools. Measured result correlates well with the simulation using ground current capturing method.


Archive | 2012

8b/9b encoding for reducing crosstalk on a high speed parallel bus

Sunil Sudhakaran; Russell R. Newcomb


international solid-state circuits conference | 2018

A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator

John M. Wilson; Walker J. Turner; John W. Poulton; Brian Zimmer; Xi Chen; Sudhir S. Kudva; Sanquan Song; Stephen G. Tell; Nikola Nedovic; Wenxu Zhao; Sunil Sudhakaran; C. Thomas Gray; William J. Dally


custom integrated circuits conference | 2018

Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects

Walker J. Turner; John W. Poulton; John M. Wilson; Xi Chen; Stephen G. Tell; Matthew R. Fojtik; Thomas H. Greer; Brian Zimmer; Sanquan Song; Nikola Nedovic; Sudhir S. Kudva; Sunil Sudhakaran; Rizwan Bashirullah; Wenxu Zhao; William J. Dally; C. Thomas Gray

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