Daehyun Chung

High frequency electrical circuit model of chip-to-chip vertical via interconnection for 3-D chip stacking package

In this paper, we firstly propose the high frequency equivalent circuit model of the chip-to-chip vertical via based on its physical configuration. The model parameters are extracted from the measurement of S-parameters using a vector network analyzer up to 20GHz frequency range. The proposed circuit model is verified experimentally in frequency and time domains. Furthermore, the high frequency characteristics of the chip-to-chip vertical via are investigated.

Near-Field and Far-Field Analyses of Alternating Impedance Electromagnetic Bandgap (AI-EBG) Structure for Mixed-Signal Applications

This paper presents near-field (NF) and far-field (FF) analysis of alternating impedance electromagnetic bandgap (AI-EBG) structure in packages and boards. Three test vehicles have been designed and fabricated for NF and FF measurements. Simulation results using a full-wave solver (SONNET) have been compared with measurement results. This paper investigates the radiation due to return current on different reference planes. The analysis results from simulations and measurements provide important guidelines for design of the AI-EBG structure based power distribution network for noise isolation and suppression in mixed-signal systems

A novel synthesis method for designing electromagnetic band gap (EBG) structures in packaged mixed signal systems

Electromagnetic (EM) simulation of electromagnetic band gap (EBG) structures is computationally expensive when multiple iterations are required. For the first time, in this paper, a novel synthesis method for designing EBG structures has been proposed. The method consists of three major approaches: current path approximation method (CPA-method), border to border radius (B2BR), and power loss method (PLM). CPA-method is based on the current flow on a periodically patterned power/ground plane. CPA-method gives a final dimension of EBG structure for a desired stop band frequency. B2BR determines the maximum number of patches implementable within a given area. PLM calculates isolation level of an EBG structure based on the transmitted power. The proposed approaches have been combined together to synthesize an EBG structure for a given specification. The synthesized EBG structure with these approaches has been fabricated and verified with EM simulation and measurement. The EBG structure has shown excellent stop band and isolation level agreements with the desired specification

Near field and far field analysis of alternating impedance electromagnetic bandgap (AI-EBG) structure for mixed-signal applications

This paper presents near field (NF) and far field (FF) analysis of alternating impedance electromagnetic bandgap (AI-EBG) structure in package and board. Three test vehicles have been designed and fabricated for near field and far field measurements. Simulation results using a full wave solver (SONNET/spl trade/) have been compared with measurement results. This paper investigates the radiation due to return current on different reference planes. The analysis results from simulations and measurements provide important guidelines for design of the AI-EBG structure for noise reduction in mixed-signal systems.

Chip-package hybrid clock distribution network and DLL for low jitter clock delivery

This paper presents a chip-package hybrid clock distribution network and delay-locked loop (DLL) with which to achieve extremely low jitter clock delivery. The proposed hybrid clock distribution network and DLL provide digital noise-free and low-jitter clock signals by utilizing lossless package layer interconnections instead of lossy on-chip global wires with cascaded repeaters. The lossless package layer interconnections become high-frequency waveguides and provide a repeater-free clock distribution network; thus, the clock signal becomes free of on-chip power supply noise. The proposed chip-package hybrid clock scheme has demonstrated a 78-ps peak-to-peak jitter at 500 MHz under a 240-mV on-chip simultaneous switching noise condition versus a conventional clock scheme, which produced a 172-ps peak-to-peak jitter under the same condition. Moreover, the proposed scheme has demonstrated an 80-ps long-term jitter with a 300-mV DC voltage drop test condition, contrasted with the 380-ps long-term jitter of a conventional clock scheme. Finally, the proposed hybrid clock scheme has a confirmed delay of 1.47 ns versus a conventional clock scheme delay of 2.85 ns.

A chip-package hybrid DLL loop and clock distribution network for low-jitter clock delivery

A chip-package hybrid DLL and clock distribution network provides low-jitter clock signals by utilizing separate supply connections and lossless package layer interconnections instead of on-chip global wires. The hybrid scheme has 78ps/sub co/ jitter and under 240mV digital noise at 500MHz, while a conventional scheme has a 172ps/sub p-p/ jitter under the same conditions.

A Three-Dimensional Stacked-Chip Star-Wiring Interconnection for a Digital Noise-Free and Low-Jitter I/O Clock Distribution Network

Cascaded repeaters are indispensable circuit elements in conventional on-chip clock distribution networks due to heavy loss characteristics of on-chip global interconnections. However, cascaded repeaters cause significant jitter and skew problems in clock distribution networks when they are affected by power supply switching noise generated by digital logic blocks located on the same die. In this letter, we present a new three-dimensional (3-D) stacked-chip star-wiring interconnection scheme to make a clock distribution network free from both on-chip and package-level power supply noise coupling. The proposed clock distribution scheme provides an extremely low-jitter and low-skew clock signal by replacing the cascaded repeaters with lossless star-wiring interconnections on a 3-D stacked-chip package. We have demonstrated a 500-MHz input/output (I/O) clock delivery with 34-ps peak-to-peak jitter and a skew of 11ps, while a conventional I/O clock scheme exhibited a 146-ps peak-to-peak jitter and a 177-ps skew in the same power supply noise environment

Effect of EBG Structures for Reducing Noise in Multi-Layer PCBs for Digital Systems

The effect of EBG structures in various noise source environments is investigated. In this paper a one-dimensional electromagnetic band gap structure (1D-EBG) has been used in the power/ground planes for isolating signal vias from noise sources. The 1D-EBG structure generates about -70dB isolation in the path between the noise source and the signal via structure, so as to minimize the coupling of the power/ground cavity noise into the signal lines. In the presence of EBG structures, the voltage noise and timing jitter are significantly reduced for periodic noise sources. However, for random noise sources, the voltage noise and timing jitter can increase in the presence of EBG structures. This paper quantifies this effect

Compensation of ESD and input capacitance effect by using package bondwire inductance for over Gbps differential SerDes devices

We firstly introduce the compensation of ICs input capacitance effect by using the package bondwire inductance. With the analysis of this effect, we suggested the methodology of finding optimized inductance and demonstrated the improvement in time-domain performance by simulation and measurement.

Overview of power/ground effects on data eye and clock jitter: from board resonance to silicon substrate coupling

In high speed digital systems, clean clock signal and data signal are guaranteed by a clean power supply network. This paper shows how power supply network affects clock jitter and data eye pattern at each power hierarchy level, that is, board level, package level, on-chip level and silicon substrate coupling level. In particular, this paper shows the most dominant factors affecting data eye and clock jitter by observing relations of each power level coincidentally.