Nikola Nedovic

Dual-edge triggered storage elements and clocking strategy for low-power systems

This paper describes the classification, detailed timing characterization, evaluation, and design of the dual-edge triggered storage elements (DETSE). The performance and power characterization of DETSE includes the effect of clocking at halved clock frequency and impact of load imposed by the storage element to the clock distribution network. The presented analysis estimates the timing penalty and power savings of a system based on DETSE, and gives design guidelines for high-performance and low-power application. In addition, the paper presents a class of dual-edge triggered flip-flops with clock load, delay, and internal power consumption comparable to the fastest single-edge triggered storage elements (SETSE). Our simulated results show that by halving the clock frequency, dual-edge clocking strategy can save about 50% of the power consumed by the clock distribution network, and relax the design of clock distribution system, while paying virtually no penalty in throughput.

Hybrid latch Flip-Flop with Improved Power Efficiency

An improved design of a hybrid latch flip-flop is presented. The proposed design overcomes the problem of the glitch at the output and reduces the power consumption and delay of the circuit resulting in a total power-delay-product improvement of about 20%. It also exhibits better soft-clock edge properties compared to the original circuit. This is accomplished by careful design of keeper elements and introducing the feedback path to suppress unnecessary transitions in the circuit. The new design introduces an insignificant area increase.

The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements

This paper represents a departure from the conventional methods of design and analysis of clocked storage elements that rely on minimizing a fixed energy-delay metric. Instead it establishes a systematic comparison in the energy-delay design space based on the parameters of the surrounding blocks. We define the composite energy-efficient characteristic over all storage element topologies and identify the most efficient storage element depending on its position on the composite characteristic relative to other topologies within a pipeline stage. Thus, we show that an optimal design could use a mixed variety of clocked storage elements (CSEs) depending on their placement in the pipeline and critical path. Since a well-designed system has hardware intensities balanced for a given cycle, a CSE choice will be made depending on the pipeline and path intensities. We show that a meaningful comparison can be carried out only by acknowledging that the optimal design and choice of the clocked storage elements depends heavily on the application, and by analyzing the energy and delay of the clocked storage elements in context of this application. The analysis in the energy-delay space allows us to understand some intuitive design choices in a quantitative way and to identify the optimal storage element topologies for an arbitrary system specification

Dynamic flip-flop with improved power

An improved design of a dynamic Flip-Flop is presented. Proposed design overcomes the problem of the glitch at the output and improves Power-Delay Product for about 10%, while preserving logic embedding property. This is accomplished by equalizing the tpLHand tpHLof the flip-flop and careful design of keeper elements in the circuit. New design introduces insignificant area increase.An improved design of a dynamic flip-flop is presented. The proposed design overcomes the problem of the glitch at the output and improves power-delay product for about 27%, while preserving logic embedding property. This is accomplished by equalizing the t/sub pLH/ and t/sub pHL/ of the flip-flop and careful design of keeper elements in the circuit. New design introduces insignificant area increase.

A clock skew absorbing flip-flop

A 0.11/spl mu/m 1.2V CMOS flip-flop absorbs up to 50ps of clock skew. Measured results confirm 27% delay and 33% energy-delay product improvement over previously reported flip-flops, regardless of clock skew.

A test circuit for measurement of clocked storage element characteristics

We present a method, on-chip test circuitry, and an error analysis, for accurate measurement of timing characteristics and power consumption of clocked storage elements. The test circuit was fabricated in 0.11 /spl mu/m CMOS technology and the measurements performed automatically using a serial scan interface. The precision and accuracy of the presented method are demonstrated by the ability to measure entire clock-to-output characteristics of flip-flops. Estimated data-to-output delay systematic measurement error is 6 ps (7%), and random error is 10 ps (11%). The method and the test circuit are applicable for delay measurements of other circuit blocks as well.

Timing characterization of dual-edge triggered flip-flops

A novel timing characterization for dual-edge triggered flip-flops is presented. This characterization takes into account the real overhead taken from the clock cycle by the flip-flops. Our study shows the correctness of these new metrics when compared against data-to-output delay. An example of the proposed delay characterization and comparison with conventional (data-to-output) metrics for dual-edge flip-flop design is given.

Conditional techniques for low power consumption flip-flops

Conditional capture and conditional precharge techniques for high-performance flip-flops are reviewed in terms of power and delay. It is found that application of conditional techniques can improve energy-delay product for up to 14% for 50% input activity and save more than 50% in power consumption for quiet input. This property makes conditional methods suitable for high-performance VLSI systems.

A 40–44 Gb/s 3

A CMOS CDR and 1:16 DEMUX fabricated in a low-cost 90 nm bulk CMOS process operates at 40-44 Gb/s and dissipates 910 mW. A quarter-rate hybrid phase-tracking/3times blind-oversampling architecture is used to improve jitter tolerance, reduce the need for high-power CML circuits, and enable frequency acquisition without a reference clock. Input data are sampled using a 24-phase distributed VCO, and a digital CDR recovers 16 bits and a 2.5 GHz clock from 48 demultiplexed samples spanning 16 UI. Conformance to the ITU-T G.8251 jitter tolerance mask (BER <10-12 with a 231-1 PRBS source) is demonstrated using both an on-chip and an external BERT.

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We present a comparison of Double-Edge Triggered clocked Storage Elements (DETSE) with their single-edge triggered counterparts in terms of delay and power consumption. In general, Latch-Mux based DETSE perform better then their single-edge counterparts while double-edge triggered flip-flops exhibit performance degradation. Up to 15% improvement in Energy-Delay Product (EDP) of Latch-Mux designs is achieved when using DETSE. The presented results indicate that the use of DETSE is a good choice when low-power operation is required.