Sunkwon Kim

42.1: A Novel Four-Mask-Count Process Architecture for TFT-LCDs

High production cost of the TFT-LCDs is closely related to the complication of the fabrication process. To simplify the fabrication process, it is critical to reduce the number of mask-count. In this paper, 4-mask-count TFT-array process using slit (or gray-tone) photolithography technology is introduced. Various kinds of the geometrical slit designs and the exposure conditions have been simulated and experimentally optimized. By adopting this novel process, TFT channel is defined without using additional photolithography.

Pattern classification of solder joint images using a correlation neural network

Abstract This paper presents a method of classifying solder joints on printed-circuit boards (PCB), using a neural-network approach. Inherently, the surface of the solder joints is curved, tiny and specularly reflective; it induces a difficulty of taking good images of the solder joints. The shapes of the solder joints tend to vary greatly with soldering conditions; solder joints, even when classified into the same soldering quality, have very different shapes. Furthermore, the position of the joints is not consistent within a registered solder pad on the PCB. Due to these aspects, it has been difficult to determine the visual features and classification criteria for automatic solder-joint inspection. In this research, the solder joints, imaged by using a circular, tiered illumination system of three colored lamps, are represented as red, green and blue colored patterns, showing their surface-slopes. Cross-correlation and auto-correlation of the colored patterns are used to classify the 3D shapes of the solder joints by their soldering qualities. To achieve this, a neural network is proposed, based on a functional link net, with two processing modules. The first preprocessing module is designed to implement the calculation of the correlations in functional terms. The subsequent, trainable module classifies the solder joints, based upon the capability learned from a human supervisor. The practical feasibility of the proposed method is demonstrated by testing numerous commercially manufactured PCBs.

18.3: Implementation of a New Wide Viewing Angle Mode for TFT-LCDs

Compare to the conventional twisted nematic (TN) mode TFT-LCD fabrication process, so far suggested method for the wide viewing angle modes require extra mask-counts. Patterning of the color filter common electrode to achieve the multi-domain vertical alignment (VA) mode costs additional process step. In addition, to avoid improper disclinations, strict alignment margin is necessary. Enhanced vertical alignment (EVA) mode has been developed where the multi-domain cell is formed by the interaction between fringe fields of the pixel electrodes and protrusions on the TFT-array panel. Compared to the TN-mode, since the common electrode is not patterned, EVA mode does not require any additional mask-count. Using the combinations of multi-layer overlap patterns with gate metal, gate dielectrics, passivation nitride, and source/drain metal, protrusions can be formed during the normal TFT-array fabrication process. Viewing angle of the EVA mode can even surpass other wide viewing modes.

A 4.8Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface

With the scaling of CMOS transistors and advance in I/O circuitry, the data rate of memory interfaces has recently reached 16Gb/s per channel [1], in which a point-to-point channel is required rather than a multi-drop channel for the high data rate. While point-to-point channels are advantageous in achieving higher data rates because of the absence of undesired reflections that occur at each stub of multi-drop channels, they are not suitable for high-capacity, high-throughput memory systems such as transaction servers or cloud computing nodes due to their prohibitively large PCB routing area connecting the memory chips. FBDIMM [2] and the cascading memory architecture [3] aim to reduce the routing area by the use of daisy-chained configurations, but they suffer from increased latency problems. This is why the recent DDR2/3 memory interface still uses the multi-drop bus architecture called stub series terminated logic (SSTL), and a number of proposals have been made to mitigate the problem of stub reflections in SSTL. For instance, a decision feedback equalizer has been used [4] to cancel the inter-symbol interference (ISI) due to stub reflections; but this requires a large number of filter taps, resulting in a limited speed under 3Gb/s. Another approach to eliminate impedance discontinuity is to use a 2Z0 ohm transmission line [5], but this scheme is only applicable to 2-slot configurations.

A visual sensing system for measuring parts deformation and misalignments in flexible parts assembly

Flexible parts compared with rigid parts can be deformed by contact force during assembly. For successful assembly, information about their deformation as well as possible misalignments between mating parts is essential. However, because of the nonlinear and complex relationship between parts deformation and reaction forces, it is difficult to acquire all the required information from the reaction forces alone. In this paper, we propose a visual sensing system for measuring parts deformation in any direction and misalignments in flexible parts assembly. This proposed system is composed of a camera and a series of mirrors, and it can overcome those self-occlusions in which a hole is occluded by mating parts. We present an algorithm that can measure parts deformation and misalignments. Simulation results show that the system is effective in measuring parts deformation and misalignments, thereby dramatically increasing the rate of success in assembly operations.

Optical Failure Analysis Technique in Deep Submicron CMOS Integrated Circuits

In this paper, we have proposed a new approach for optical failure analysis which employs a CMOS photon-emitting circuitry, consisting of a flip- flop based on a sense amplifier and a photon-emitting device. This method can be used even with deep- submicron processes where conventional optical failure analyses are difficult to use due to the low sensitivity in the near infrared (NIR) region of the spectrum. The effectiveness of our approach has been proved by the failure analysis of a prototype designed and fabricated in 0.18 μm CMOS process.

A comparator-based cyclic analog-to-digital converter with boosted preset voltage

In this paper, we describe a cyclic ADC to adopt the comparator-based switched-capacitor (CBSC) technique, for the first time, so as to compensate for the technology scaling and reduce power consumption by eliminating the need for high gain opamps. A boosted preset voltage is also introduced to improve the conversion rate without consuming more power. The ADC operates at 2.5MS/s, and near the Nyquist-rate, a prototype has a signal-to-noise and distortion ratio (SNDR) of 55.99 dB and a spurious-free dynamic-range (SFDR) of 66.85 dB. The chip was fabricated in 0.18μm CMOS and it has an active area of 0.146mm2 and consumes 0.74mW from a 1.8V supply.

A CMOs readout integrated circuit with wide dynamic range for a CNT bio-sensor array system

We present a sensor readout integrated circuit for the CNT bio-sensor array, the heart of which is our low-power current-input continuous-time ΔΣ modulator that is capable of dynamic range extension. Experimental results show that the prototype chip, designed and fabricated in 0.18μm CMOS process, achieves a dynamic range of 87.746dB and has a readout rate of 160kHz, which guarantees 1k sample/s per each sensor. It consumes 8.94μW/cell considering the 16×10 sensors and its core area is 0.085mm2.

A low-power referenceless clock and data recovery circuit with clock-edge modulation for biomedical sensor applications

This paper proposes a low-power referenceless clock and data recovery (CDR) circuit for biomedical devices or sensor applications. Its power consumption is reduced by adopting clock-edge modulation technique and using a voltage-controlled oscillator (VCO) based on a relaxation oscillator. Clock-edge modulation eliminates the need for an external reference clock without introducing the possibility of harmonic locking. Our CDR supports input data-rates between 200kbps and 10Mbps at 0.7V, and operate up to 24 MHz at 1.0V. The circuit is designed in a 0.18μm CMOS technology and consumes 8μW at an input data-rate of 10Mbps.

Neural recording system with low-noise analog front-end and comparator-based cyclic ADC

This paper describes a low-noise neural recording integrated circuit composed of a low-noise analog front-end (AFE) and a low-power analog-to-digital converter (ADC). The AFE amplifies biopotentials and the ADC converts input signal to digital output. The AFE exhibits 53.4dB of mid-band gain, 38.8Hz-10.6kHz of -3dB bandwidth. Total input referred noise (IRN) of AFE is 10.8μVrms and noise efficiency factor (NEF) is 8.1. The ADC achieves 10bit resolution and operates at 2.5MS/s. The chip is fabricated and successfully tested in a 0.18μm CMOS process.