Hyunjoong Lee

A Delta–Sigma Interface Circuit for Capacitive Sensors With an Automatically Calibrated Zero Point

We present a low-complexity interface circuit for capacitive sensors that are integrated into sensor microsystems. To reduce hardware cost while keeping high resolution, a first-order delta-sigma modulator (DSM), which balances the charge from the capacitive difference between sense and reference capacitors with the charge from a fixed-quantity capacitor, is employed. A charge-mode digital-to-analog converter and a successive approximation register are utilized to automatically calibrate the zero point of the interface circuit, which may shift further than a dynamic range. A prototype circuit fabricated in a 0.35-μm CMOS process has an active area of 0.048 mm2. Its DSM operates at a sampling frequency of 1 MS/s with an oversampling ratio of 128. Experiments show that this circuit can read a capacitive difference from -0.5 to +0.5 pF with a 0.49-fF resolution. A capacitive offset that causes the zero point to shift can be canceled in the range from -2 to 2 pF with a 31.25-fF resolution. Measured power consumption was 1.44 mW at a 3.3-V supply.

Biosensor system-on-a-chip including CMOS-based signal processing circuits and 64 carbon nanotube-based sensors for the detection of a neurotransmitter

We developed a carbon nanotube (CNT)-based biosensor system-on-a-chip (SoC) for the detection of a neurotransmitter. Here, 64 CNT-based sensors were integrated with silicon-based signal processing circuits in a single chip, which was made possible by combining several technological breakthroughs such as efficient signal processing, uniform CNT networks, and biocompatible functionalization of CNT-based sensors. The chip was utilized to detect glutamate, a neurotransmitter, where ammonia, a byproduct of the enzymatic reaction of glutamate and glutamate oxidase on CNT-based sensors, modulated the conductance signals to the CNT-based sensors. This is a major technological advancement in the integration of CNT-based sensors with microelectronics, and this chip can be readily integrated with larger scale lab-on-a-chip (LoC) systems for various applications such as LoC systems for neural networks.

A Process-Variation-Tolerant On-Chip CMOS Thermometer for Auto Temperature Compensated Self-Refresh of Low-Power Mobile DRAM

Smaller transistors mean that capacitors are charged less uniformly, which increases the self-refresh current in the DRAMs used in mobile devices. Adaptive self-refresh using an on-chip thermometer can solve this problem. We propose an on-chip CMOS thermometer specifically designed for controlling the refresh period of a DRAM. This thermometer includes a novel temperature sensor which has been implemented and integrated into an LPDDR2 chip. The LPDDR2 chip is fabricated in a 44-nm DRAM process. The sensor has a temperature sensitivity of -3.2 mV/°C, over a range of 0°C to 110°C. Its resolution is 1.94°C and is only limited by the 6.2-mV step of the associated resistor ladder not by its own design. The linearity of the sensor permits one-point calibration, after which the errors in 61 sample circuits ranged between -1.42°C and +2.66°C. The sensor has an active area of 0.001725 mm2 and consumes less than 0.36 μW on average with a supply of 1.1 V. At its lowest operating temperature, this thermometer reduces the IDD6 current of the LPDDR2 chip by almost half.

A 14.6 ps Resolution, 50 ns Input-Range Cyclic Time-to-Digital Converter Using Fractional Difference Conversion Method

This paper presents a time-to-digital converter (TDC) using a fractional difference conversion scheme. Two delay-locked loops (DLLs) provide negative feedbacks to stabilize the delays against process and ambient variations. In addition, by adopting the principles of cyclic Vernier delay line, the resolution is improved while dynamic range is significantly increased. The proposed TDC architecture is competitive in terms of resolution and power compared to the other DLL/PLL stabilized TDCs. The TDC designed and fabricated in 0.18 μm CMOS process achieves a 14.6 ps resolution as well as a 50 ns dynamic range, while consuming 6.4 mW power.

A Low-Cost and Low-Power Time-to-Digital Converter Using Triple-Slope Time Stretching

In this brief, we present a time-to-digital converter (TDC) in which a single interpolator is used to improve the resolution by time stretching. The interpolator is based on a triple-slope conversion. Without slowing down the measured event, this approach extensively reduces the chip area and the corresponding power consumption, as compared with the prior arts with two parallel time interpolators. A prototype was designed and fabricated in a 0.35- μm CMOS digital process, and its core area merely occupies 0.126 mm2. Measurements show that our TDC achieves a resolution of 357 ps while consuming 1.22 mW with a 2.5-V supply. The dynamic range of the TDC exceeds 1.46 μs. The measurement rate can achieve above 400 kS/s.

A Fast-Locking CDR Circuit with an Autonomously Reconfigurable Charge Pump and Loop Filter

This paper presents the design of a phase-locked loop (PLL) based clock and data recovery (CDR) circuit that meets fast locking and low jitter. We reduce the locking time of a CDR circuit using a new autonomously reconfigurable charge pump and loop filter in a 1.25 Gb/s CDR circuit. An experimental prototype was implemented in a 0.18 mum standard CMOS technology. A receiver that incorporates our CDR circuit has an active area of 380 mum times 350 mum.

Optical Failure Analysis Technique in Deep Submicron CMOS Integrated Circuits

In this paper, we have proposed a new approach for optical failure analysis which employs a CMOS photon-emitting circuitry, consisting of a flip- flop based on a sense amplifier and a photon-emitting device. This method can be used even with deep- submicron processes where conventional optical failure analyses are difficult to use due to the low sensitivity in the near infrared (NIR) region of the spectrum. The effectiveness of our approach has been proved by the failure analysis of a prototype designed and fabricated in 0.18 μm CMOS process.

Improving the Accuracy of Capacitance-to-Frequency Converter by Accumulating Residual Charges

Recently, capacitive sensors, which consist of a sense capacitor and a reference capacitor, have been considered for a sensor array for monitoring biomolecular reactions. Although a capacitance-to-frequency converter (CFC) may be a simple and effective solution for reading a capacitive difference between the sensor capacitors, prior versions lack sufficient accuracy. In this paper, we present a more accurate CFC, which produces a single pulse stream in a wide range of frequencies. This circuit saves residual charges and accumulates them when discharging an integrator capacitor. Implemented in 0.35-μm CMOS technology, our circuit improves the accuracy from about 6% to 0.13 %.

Power-Gating Noise Minimization by Three-Step Wake-Up Partitioning

Power gating is able to counter subthreshold leakage in low-power nanometer technology circuits without sacrificing performance. But mode transitions in power-gated circuits are accompanied by large inrush/discharge currents causing inductive bounce noise on the power supply and ground rails. This issue has been addressed by gradually turning on the sleep transistor; but this introduces a fixed lower bound on the delay overhead irrespective of the duration of the sleep period, and takes no account of the effects of changes in the circuit internal nodes during wake-up on the ground bounce noise. We observed the behavior of internal nodes during the sleep-to-active mode transition and identified three distinct stages. This motivates a three-step turn-on scheme and an associated compact power-gating structure that limits the current flowing through the sleep transistor only while the gated block is metastable, but quickly boosts the power supply rail when there are no short-circuit current paths in the logic. This strongly suppresses power gating noise, and also reduces wake-up time. Simulation results of 16-bit arithmetic logic units in 65-nm CMOS technology show that the proposed technique offers the advantage of a wake-up time that scales with the discharged value (during sleep) of the virtual power rail.

A comparator-based cyclic analog-to-digital converter with boosted preset voltage

In this paper, we describe a cyclic ADC to adopt the comparator-based switched-capacitor (CBSC) technique, for the first time, so as to compensate for the technology scaling and reduce power consumption by eliminating the need for high gain opamps. A boosted preset voltage is also introduced to improve the conversion rate without consuming more power. The ADC operates at 2.5MS/s, and near the Nyquist-rate, a prototype has a signal-to-noise and distortion ratio (SNDR) of 55.99 dB and a spurious-free dynamic-range (SFDR) of 66.85 dB. The chip was fabricated in 0.18μm CMOS and it has an active area of 0.146mm2 and consumes 0.74mW from a 1.8V supply.