Hyongmin Lee

A 4.8Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface

With the scaling of CMOS transistors and advance in I/O circuitry, the data rate of memory interfaces has recently reached 16Gb/s per channel [1], in which a point-to-point channel is required rather than a multi-drop channel for the high data rate. While point-to-point channels are advantageous in achieving higher data rates because of the absence of undesired reflections that occur at each stub of multi-drop channels, they are not suitable for high-capacity, high-throughput memory systems such as transaction servers or cloud computing nodes due to their prohibitively large PCB routing area connecting the memory chips. FBDIMM [2] and the cascading memory architecture [3] aim to reduce the routing area by the use of daisy-chained configurations, but they suffer from increased latency problems. This is why the recent DDR2/3 memory interface still uses the multi-drop bus architecture called stub series terminated logic (SSTL), and a number of proposals have been made to mitigate the problem of stub reflections in SSTL. For instance, a decision feedback equalizer has been used [4] to cancel the inter-symbol interference (ISI) due to stub reflections; but this requires a large number of filter taps, resulting in a limited speed under 3Gb/s. Another approach to eliminate impedance discontinuity is to use a 2Z0 ohm transmission line [5], but this scheme is only applicable to 2-slot configurations.

Optical Failure Analysis Technique in Deep Submicron CMOS Integrated Circuits

In this paper, we have proposed a new approach for optical failure analysis which employs a CMOS photon-emitting circuitry, consisting of a flip- flop based on a sense amplifier and a photon-emitting device. This method can be used even with deep- submicron processes where conventional optical failure analyses are difficult to use due to the low sensitivity in the near infrared (NIR) region of the spectrum. The effectiveness of our approach has been proved by the failure analysis of a prototype designed and fabricated in 0.18 μm CMOS process.

Differentiating ASK Demodulator for Contactless Smart Cards Supporting VHBR

This brief proposes an amplitude shift keying (ASK) demodulator that uses switched-capacitor differentiators to make it compliant with the very high bit rate amendment to the ISO/IEC 14443 standard for contactless smart card applications. These differentiators detect transitions in modulated ASK signals with a carrier frequency of 13.56 MHz at data rates up to 6.78 Mb/s. The demodulator has been implemented in 0.18 μm CMOS technology. The total power consumption is under 350 μW. Measured results confirm correct operation, and it is further shown that this differentiating scheme allows the modulation index to be reduced to 2.56%.

A comparator-based cyclic analog-to-digital converter with boosted preset voltage

In this paper, we describe a cyclic ADC to adopt the comparator-based switched-capacitor (CBSC) technique, for the first time, so as to compensate for the technology scaling and reduce power consumption by eliminating the need for high gain opamps. A boosted preset voltage is also introduced to improve the conversion rate without consuming more power. The ADC operates at 2.5MS/s, and near the Nyquist-rate, a prototype has a signal-to-noise and distortion ratio (SNDR) of 55.99 dB and a spurious-free dynamic-range (SFDR) of 66.85 dB. The chip was fabricated in 0.18μm CMOS and it has an active area of 0.146mm2 and consumes 0.74mW from a 1.8V supply.

A CMOs readout integrated circuit with wide dynamic range for a CNT bio-sensor array system

We present a sensor readout integrated circuit for the CNT bio-sensor array, the heart of which is our low-power current-input continuous-time ΔΣ modulator that is capable of dynamic range extension. Experimental results show that the prototype chip, designed and fabricated in 0.18μm CMOS process, achieves a dynamic range of 87.746dB and has a readout rate of 160kHz, which guarantees 1k sample/s per each sensor. It consumes 8.94μW/cell considering the 16×10 sensors and its core area is 0.085mm2.

A low-power referenceless clock and data recovery circuit with clock-edge modulation for biomedical sensor applications

This paper proposes a low-power referenceless clock and data recovery (CDR) circuit for biomedical devices or sensor applications. Its power consumption is reduced by adopting clock-edge modulation technique and using a voltage-controlled oscillator (VCO) based on a relaxation oscillator. Clock-edge modulation eliminates the need for an external reference clock without introducing the possibility of harmonic locking. Our CDR supports input data-rates between 200kbps and 10Mbps at 0.7V, and operate up to 24 MHz at 1.0V. The circuit is designed in a 0.18μm CMOS technology and consumes 8μW at an input data-rate of 10Mbps.

MATLAB/Simulink Pulse-Echo Ultrasound System Simulator Based on Experimentally Validated Models

A flexible clinical ultrasound system must operate with different transducers, which have characteristic impulse responses and widely varying impedances. The impulse response determines the shape of the high-voltage pulse that is transmitted and the specifications of the front-end electronics that receive the echo; the impedance determines the specification of the matching network through which the transducer is connected. System-level optimization of these subsystems requires accurate modeling of pulse-echo (two-way) response, which in turn demands a unified simulation of the ultrasonics and electronics. In this paper, this is realized by combining MATLAB/Simulink models of the high-voltage transmitter, the transmission interface, the acoustic subsystem which includes wave propagation and reflection, the receiving interface, and the front-end receiver. To demonstrate the effectiveness of our simulator, the models are experimentally validated by comparing the simulation results with the measured data from a commercial ultrasound system. This simulator could be used to quickly provide system-level feedback for an optimized tuning of electronic design parameters.

A 9-bit, 110-MS/s pipelined-SAR ADC using time-interleaved technique with shared comparator

A 9-bit 110-MS/s pipelined-SAR ADC is proposed. To alleviate the design tradeoff between conversion rate and power consumption, the design adopts a voltage-mode open-loop amplifier and a time-interleaved SAR architecture with comparator sharing. The ADC simulated in a 65-nm CMOS technology achieves an ENOB of 8.63 bits near the Nyquist input frequency at the sampling rate of 110MS/s. The power consumption is 7.9mW, resulting in 181.3fJ/conversion-step of Figure of Merit (FoM).

A behavioral model of a two-stage average-current-mode-controlled PFC converter for dimmable MR16 LED lamps

MR16 LED retrofit lamps can be made compatible with legacy dimmers by using drivers that employ power factor correction (PFC) to imitate a resistive load, and detect the conduction angle for dimming control. One possible design is a two-stage switching converter, in which the first stage performs PFC as well as detecting the conduction angle, and the second stage drives the LED, which is dimmed in proportion to the detected conduction angle. In this work, we modeled a driver circuit for dimmable MR16 LED lamps and verified operation of the design with different conduction angles through simulation.

A 32-channel neural recording system with a liquid-crystal polymer MEA

Our integrated 32-channel recording system for in-vivo measurement of neural activity has 32 analog front-end (AFE) channels, a 32-to-1 time-division multiplexer, and a comparator-based cyclic ADC. Each channel has a low noise amplifier and a programmable-gain amplifier (PGA) with a tunable bandwidth. The mid-band gain of the low noise amplifier is 47 dB. The total gain of the analog front-end is adjustable from 54 dB to 67 dB, and its input-referred noise is 11.93 μVrms. The low noise amplifier consumes 7.2 μW per channel. The comparator-based cyclic ADC digitizes the signals at 20 kS/s per channel, with a signal to distortion and noise ratio (SNDR) of 48.23 dB, corresponding to an effective number of bits (ENOB) of 7.72. This system was implemented in 0.18 μm CMOS technology, the average power consumption of the system is 62.5 μW per channel. An in-vivo measurement of the electrical activity of the cerebral cortex has been demonstrated, using a flexible liquid-crystal polymer microelectrode array.