Suraj Sindia

A Test Time Theorem and its Applications

Power dissipated during test is a constraint when it comes to test time reduction. In this work, we show that for a given test the minimum test application time is achieved when the total energy is dissipated evenly at the rate of the maximum allowable power for the device under test. This result, the test time theorem, leads to two alternatives for reducing test time. In the first alternative, we scale the supply voltage down to reduce power, which in turn allows us to increase the clock frequency, of course within the limit imposed by the critical path. Thus, optimum voltage and frequency can be found to minimize the test time of a fixed frequency synchronous test. In the other alternative, which also benefits from the reduced voltage, the clock period is dynamically varied so that each cycle dissipates the maximum allowable power. This test, termed aperiodic clock test, according to the theorem achieves the lower bound on test time. An illustrative example of an ISCAS’89 benchmark circuit shows a test time reductionof 71 %.

Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients

A method of testing for parametric faults of analog circuits based on a polynomial representation of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the applied input voltage at relevant frequencies in addition to DC. Classification of CUT is based on a comparison of the estimated polynomial coefficients with those of the fault free circuit. This testing method requires no design for test hardware as might be added to the circuit by some other methods. The proposed method is illustrated for a benchmark elliptic filter. It is shown to uncover several parametric faults causing deviations as small as 5% from the nominal values.

Test and Diagnosis of Analog Circuits Using Moment Generating Functions

The function of a circuit under test (CUT) is represented as a transformation on the probability density function of its input excitation, which is a continuous random variable (RV) with Gaussian probability distribution. Probability moments of the output, now a transformed RV, are used as metrics for testing catastrophic and parametric faults in circuit components. The proposed use of probability moments as test metrics with white noise excitation as input addresses three important problems of analog circuit test, namely, it 1) reduces complexity of input signal design, 2) increases resolution of fault detection, and 3) reduces production test cost as it has no area overhead and may even marginally reduce the test time. We also propose a method to diagnose circuit elements with catastrophic faults based on unique relationships between specific moments of the output and circuit elements. We present a theoretical framework, test and diagnosis procedures and SPICE simulation results for a benchmark elliptic filter and a low noise amplifier. We are able to detect all catastrophic faults and single components that deviate from their nominal values by just over 10%. We diagnose all catastrophic faults in the example circuits.

MobSched: Customizable scheduler for mobile cloud computing

In this paper, we explore how cloud computing techniques can be used on mobile devices. We analyze the reason why Hadoops performance is poor in MANET, most notably, relying too much on distributed filesystem, and not aware of mobility and multi-hop nature of MANET. Two ways are proposed to deploy mobile cloud computing in an efficient manner: MobSched, a customizable job scheduler; and a mobile friendly MapReduce framework. These two methods enable developers to use MapReduce programming model in the context of MANET. Theoretical analysis suggests that the proposed framework can improve the performance of MapReduce jobs running on top of MANET, and reduce the energy consumption. Simulation results show that the proposed scheduler, MobSched, which is based on a linear programming formulation, can efficiently optimize multiple objectives such as power and (or) throughput, while being constrained with requirements such as minimum quality of service, and (or) maximum bandwidth usage that has to be met by the system. Comparison with other schedulers such as uniform load balancing, FIFO, and clustering types show that the proposed scheduler performs best when it comes to optimizing for a specific criteria such as total power consumption within reasonable latency.

Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients

We propose a method for diagnosis of parametric faults in analog circuits using polynomial coefficients of the circuit model [15]. As a sequel to our recent work [14], where circuit response is modeled as polynomial for uncovering parametric faults in nonlinear circuits, we propose diagnosis of such faults using sensitivity of coefficients of the estimated polynomial to circuit parameters. The proposed method requires no design for test hardware as might be added to the circuit by some other methods. The proposed method is illustrated for a benchmark elliptic filter. It is shown to uncover several parametric faults causing deviations as small as 5% from the nominal values.

A test time theorem and its applications

We prove a theorem stating that the test time of digital test is obtained upon dividing the total energy dissipated during test by the average rate of consumption or power. As we try to reduce the test time, the critical path delay (structural constraint) and the peak power capability of the circuit (power constraint) limit our capability to increase the rate of energy consumption. The theorem leads to two modes of testing, namely, synchronous and asynchronous. Supply voltage plays a significant role in optimizing the test time.

Tailoring Tests for Functional Binning of Integrated Circuits

In recent years, a number of high level applications have been reported to be tolerant to errors resulting from a sizable fraction of all single stuck-at faults in hardware. Production testing of devices targeted towards such applications calls for a test vector set that is tailored to maximize the coverage of faults that lead to functionally malignant errors while minimizing the coverage of faults that produce functionally benign errors. Given a partitioning of the fault set as benign and malignant, and a complete test vector set that covers all faults, in this paper, we formulate an integer linear programming (ILP) problem to find an optimal test vector set that ensures 100% coverage of malignant faults and minimizes coverage of benign faults.We also propose a test strategy based on selectively masking appropriate outputs of the circuit to partition the circuits at production test into three bins - malignant, benign, and fault-free. As a case study, we demonstrate the proposed ILP based test optimization and functional binning on three adder circuits: 16-bit ripple carry adder, 16-bit carry lookahead adder, and 16-bit carry select adder. We find that the proposed ILP based optimization gives a reduction of about 90% in fault coverage of benign faults while ensuring 100% coverage of malignant faults. This typically translates to an (early manufacturing) yield improvement of over 20% over what would have been the yield if both malignant and benign faults are targeted without distinction by the test vectorset.

Impact of process variations on computers used for image processing

Manufacturing process variations (PV) of transistors in the deep-submicron regime present the single biggest design challenge for large die size VLSI circuits such as processor arrays, GPUs, and FPGAs. However, there are a few applications in signal processing, such as image processing, and speech processing, where errors in computation by the underlying hardware could be tolerated or corrected off-line with readily available image restoration algorithms. In this paper, we qualitatively and quantitatively evaluate the effect of process variation in the underlying hardware (for different technology nodes) on a high level application program such as image processing. We rely on gate level simulation, of the data-path of an image processor comprising of a dedicated multiply-accumulate (MAC) array of size 256 × 256, with individual gate delays of the processor sampled from a delay distribution as appropriate for each technology node. Our results show that processing images with PV degraded hardware in technologies beyond 65nm is discernible to the human eye; image quality degrades further at 45nm, and is of unacceptable quality at 32nm and beyond. We also use image restoration algorithms to restore the images corrupted due to processing on PV degraded hardware. Our results show that with standard restoration algorithms, even images processed with high levels of PV (as in 32nm) can be restored to almost the same quality as the image processed on fault-free hardware.

Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients

Parametric fault testing of non-linear analog circuits based on a new mathematical transform is presented. The V-Transform acts on the polynomial expansion of the circuits function. Its main properties are: 1) to make the polynomial coefficients monotonic, 2) to reduce masking of parametric faults due to process variation, and 3) to increase the sensitivity of polynomial coefficients to the circuit parameter variation, thus enhancing diagnostic resolution. We show that the sensitivity of V-Transform Coefficients (VTC) with respect to circuit parameter variation is up to 3 to 5 times greater than the sensitivity of polynomial coefficients. Fault diagnosis of parametric faults under process variation using VTC is then presented. We also propose a scheme to distinguish between circuit specifications failures due to process variation versus manufacturing defects which manifest as parametric faults. To validate our approach, we apply the test and diagnosis procedures to a benchmark fifth order elliptic filter. We use SPICE program for fault injection, with about 50,000 Monte Carlo simulation runs to demonstrate fault detection-diagnosis under process variation. The test scheme uncovers 95% of all injected single parametric faults whose sizes deviate 5% from the nominal values of circuit components corrected for process variation, while the procedure successfully diagnosed all component faults under ±3σ process variation with 88% confidence level.

Testing linear and non-linear analog circuits using moment generating functions

Circuit under test (CUT) is treated as a transformation on the probability density function of its input excitation, which is, a continuous random variable (RV) of gaussian probability distribution. Probability moments of the output, which is now the transformed RV, is used as a metric for testing catastrophic and parametric faults in circuit components that make up the CUT. Use of probability moments as circuit test metric with white noise excitation as input addresses three important problems faced in analog circuit test, namely: 1) Reduces complexity of input signal design, 2) Increases resolution of fault detection, and 3) Reduces production test cost as it has no area overhead and marginally reduces test time. We develop the theory, test procedure and report SPICE simulation results of the proposed scheme on a benchmark elliptic filter. With the proposed scheme, we are able to detect all catastrophic faults and single parametric faults that are off from their nominal value by just over 10%. Method reported in this paper paves way for future research in circuit diagnosis, leveraging moments of the output to diagnose parametric faults in analog circuits.