Surajit Sutar

Angle-Dependent Carrier Transmission in Graphene p–n Junctions

Angle-dependent carrier transmission probability in graphene p-n junctions is investigated. Using electrostatic doping from buried gates, p-n junctions are formed along graphene channels that are patterned to form different angles with the junction. A peak in the junction resistance is observed, which becomes pronounced with angle. This angular dependence is observed for junctions made on both exfoliated and CVD-grown graphene and is consistent with the theoretically predicted dependence of transmission probability on incidence angle.

Reconfigurable p-n junction diodes and the photovoltaic effect in exfoliated MoS2 films

Realizing basic semiconductor devices such as p-n junctions are necessary for developing thin-film and optoelectronic technologies in emerging planar materials such as MoS2. In this work, electrostatic doping by buried gates is used to study the electronic and optoelectronic properties of p-n junctions in exfoliated MoS2 flakes. Creating a controllable doping gradient across the device leads to the observation of the photovoltaic effect in monolayer and bilayer MoS2 flakes. For thicker flakes, strong ambipolar conduction enables realization of fully reconfigurable p-n junction diodes with rectifying current-voltage characteristics, and diode ideality factors as low as 1.6. The spectral response of the photovoltaic effect shows signatures of the predicted band gap transitions. For the first excitonic transition, a shift of >4kBT is observed between monolayer and bulk devices, indicating a thickness-dependence of the excitonic coulomb interaction.

Bistable-Body Tunnel SRAM

A one-transistor tunnel static random access memory (SRAM) cell is proposed and analyzed. The new cell uses the bistability of a tunnel diode pair to latch the body voltage of a MOSFET that then shifts the threshold voltage and enables sensing of the state by the measurement of the MOSFET transistor current. Band-to-band tunneling is used to write the cell. This cell offers more than 10 000× reduction in static power compared to the 6-transistor (T) SRAM at the 32-nm technology node. A cell size of 48F2 is shown, which is comparable to a 6-T SRAM. Access times should be similar to high performance a 6-T SRAM given the same transistor technology.

One-transistor bistable-body tunnel SRAM

A one-transistor tunnel SRAM cell is proposed and analyzed. The new cell uses the bistability of a tunnel diode pair to latch the body voltage of a MOSFET which then shifts the threshold voltage and enables sensing of the state by measurement of the MOS transistor current. Band-to-band tunneling is used to write the cell.

Structural Sensitivity of Interband Tunnel Diodes for SRAM

Here, we present a study to outline the design space and trade-offs for high PVCR, low-voltage, low-current tunnel diodes with best results for peak currents and voltages being 4.3 nA/mum2, 50 mV with PVCR of 15, and demonstrate a fabrication process yielding submicron interband tunnel diodes for the first time. The PVCR of submicron diodes is observed to degrade for submicron device mesas indicating the need for passivation to maintain the PVCR.

InAlAs/InGaAs Interband Tunnel Diodes for SRAM

The dependence of doping and alloy composition in InGaAs/InAlAs double-quantum-well resonant interband tunnel diodes (TDs) for static random access memory (SRAM) applications is explored. The peak current density is shown to vary by 5 orders of magnitude as the effective doping density is varied by a factor of 5. The reasons for this dependence are determined by characterization and analysis of current-voltage-temperature and capacitance-voltage measurements. This paper demonstrates a low-current bistable TD pair for SRAM with peak current density of 4 nA/μm2, peak-to-valley current ratio of 14, and peak voltage of 0.05 V enabling static binary storage at a supply voltage as low as 0.25 V.

Rapid melt growth of Ge tunnel junctions for interband tunnel transistors

In this paper, the authors report on the simulated characteristics of Ge interband tunnel transistors and show the first characteristics of submicron p⁺n⁺ junction tunnel junctions using rapid melt growth of Ge. This process uses a phosphorus spin-on diffusant followed by rapid thermal annealing to form the n layer. Aluminum is then deposited by lift-off, capped with Si₃N₄, and liquified in a rapid thermal processor to dissolve back and regrow the p⁺ side of the tunnel junction.

Incidence angle-dependent transport across a single graphene p-n junction

Graphene p-n junction (GPNJ) can be used to build logic, using the incidence-angle-dependent carrier transmission [1]. This report presents a method to gate Graphene by buried split-gates (SG) which enable precise control of the doping profiles by the SG spacing. The main result of the report is that even at T = 300K and modest graphene mobility, the GPNJ resistance shows a significant variation with incidence angle, indicating carrier chirality effects.

Tunnel diode/transistor differential comparator

A new tunnel diode/transistor circuit topology is reported, which both increases speed and reduces power in differential comparators. This circuit topology is of special interest for use in direct digital synthesis applications. The circuit topology can be extended to provide performance improvements in high speed logic and signal processing applications. The circuits are designed based on InP/GaAsSb double heterojunction bipolar transistors and AlAs/InGaAs/AlAs resonant tunneling diodes. A self-aligned and scalable fabrication approach using nitride sidewalls and chemical mechanical polishing is outlined.