Kamal M. Karda

Polarization‐engineering in group III‐nitride heterostructures: New opportunities for device design

The role of spontaneous and piezoelectric polarization in III-V nitride heterostructure devices is discussed. Problems as well as opportunities in incorporating polarization in abrupt and graded heterojunctions composed of binary, ternary, and quaternary nitrides are outlined.

Process integration of a 27nm, 16Gb Cu ReRAM

A 27nm 16Gb Cu based NV Re-RAM chip has been demonstrated. Novel process introduction to enable this technology include a Damascene Cell, Line-SAC Digit Lines filled with Cu, exhumed-silicided array contacts, raised epitaxial arrays, and high-drive buried access devices.

Bistable-Body Tunnel SRAM

A one-transistor tunnel static random access memory (SRAM) cell is proposed and analyzed. The new cell uses the bistability of a tunnel diode pair to latch the body voltage of a MOSFET that then shifts the threshold voltage and enables sensing of the state by the measurement of the MOSFET transistor current. Band-to-band tunneling is used to write the cell. This cell offers more than 10 000× reduction in static power compared to the 6-transistor (T) SRAM at the 32-nm technology node. A cell size of 48F2 is shown, which is comparable to a 6-T SRAM. Access times should be similar to high performance a 6-T SRAM given the same transistor technology.

One-transistor bistable-body tunnel SRAM

A one-transistor tunnel SRAM cell is proposed and analyzed. The new cell uses the bistability of a tunnel diode pair to latch the body voltage of a MOSFET which then shifts the threshold voltage and enables sensing of the state by measurement of the MOS transistor current. Band-to-band tunneling is used to write the cell.