Susan G. Cann

Line-edge roughness in sub-0.18-μm resist patterns

We have characterized line-edge roughness in single-layer, top-surface imaging, bilayer and trilayer resist schemes. The results indicate that in dry developed resists there is inherent line-edge roughness which results from the etch mask, resist (planarizing layer) erosion, and their dependence on plasma etch conditions. In top surface imaging the abruptness of the etch mask, i.e., the silylation contrast, and the silicon content in the silylated areas are the most significant contributors to line-edge roughness. Nevertheless, even in the case of a trilayer, where the SiO2 layer represents the near ideal mask, there is still resist sidewall roughness of the planarizing layer observed which is plasma induced and polymer dependent. The mechanism and magnitude of line-edge roughness are different for different resist schemes, and require specific optimization. Plasma etching of silicon, like O2 dry development, contributes to the final line-edge roughness of patterned features.

Hybrid optical maskless lithography: Scaling beyond the 45nm node

Optical lithography at 193nm with resolution enhancements and immersion is widely expected to meet the needs of the 45nm node. Beyond this, at 32nm and below, the solution is not as clear. In this article we present simulation results and experimental demonstrations of an all-optical approach capable of high-throughput 32nm lithography (hybrid optical maskless lithography). In this method high-resolution dense gratings are defined in a first exposure using maskless interference lithography. A second “trim” exposure, using conventional projection lithography, customizes these gratings into useful patterns. Our simulations indicate that 32nm node patterning can be achieved using trim tools and masks of significantly lower resolution. We also present experimental feasibility results using 157nm “dry” interference in combination with projection 248nm or e-beam trim exposures. The technological requirements and extendibility of such a method beyond the 32nm node are also examined.

Gratings of regular arrays and trim exposures for ultralarge scale integrated circuit phase-shift lithography

Current semiconductor technology requires optical lithography to image feature sizes smaller than the exposure tool wavelength. In order to achieve this subwavelength imaging, some form of optical resolution-enhancement technology is required, with phase-shift methods offering the greatest potential enhancement. Major impediments to the wide-scale adoption of this technology have included mask cost, inspectability/repair, and turnaround time. The correction of optical proximity effects, which are typically large in phase-shift techniques, have also been an important issue. In this work, we propose a new type of phase-shift approach utilizing gratings of regular arrays and trim exposures. This method makes use of multiple-exposure phase-shift imaging of dense-only features. Proximity effects can be nearly eliminated along with the complex optical proximity corrections typically required on the mask. The simple phase-shift masters can also be reused for multiple designs, thereby addressing cost and turnarou...

Sub-100 nm silicon on insulator complimentary metal–oxide semiconductor transistors by deep ultraviolet optical lithography

We report results on the fabrication of deep sub-100 nm silicon-on-insulator (SOI) complimentary metal–oxide semiconductor transistors using phase-shift double-exposure deep ultraviolet optical lithography. Resist gate features down to 40 nm were resolved corresponding to λ/6 resolution or k1=0.1. Using an etch bias, we have fabricated polysilicon gate features down to 25 nm corresponding to λ/10 resolution or k1=0.06. Good process latitudes were obtained, and SOI transistor results down to 50 nm gate length are reported.

Contributions of resist polymers to innate material roughness

The authors have extended the atomic force microscopy-based technique to measure intrinsic material roughness after base development to evaluate a number of different polymer types in resist formulations. These polymers include environmentally stable chemical amplified photoresist type copolymers and terpolymers, methacrylate polymers, and fluoropolymers. The surface roughness of resists containing these polymers was measured along with the clearing dose with both extreme ultraviolet (EUV) and deep ultraviolet (DUV) exposures. Selected resists containing a representative sampling of different lithographic polymers were imaged with both EUV and DUV exposures. It has been suggested by many that there is a fundamental inverse relationship between resist sensitivity and LER that leads to a fundamental limit to resist performance. It was found that no simple relationship exists between intrinsic material roughness (IMR) and sensitivity and instead some other, more complex relationship between the material properties of the polymer and resist process that is determining both the IMR and sensitivity. It was also found that no simple relationship existed between resist sensitivity and LER. This suggests that resist performance is not innately limited by any fundamental law but is instead open to further improvements through the use of new materials or material combinations.The authors have extended the atomic force microscopy-based technique to measure intrinsic material roughness after base development to evaluate a number of different polymer types in resist formulations. These polymers include environmentally stable chemical amplified photoresist type copolymers and terpolymers, methacrylate polymers, and fluoropolymers. The surface roughness of resists containing these polymers was measured along with the clearing dose with both extreme ultraviolet (EUV) and deep ultraviolet (DUV) exposures. Selected resists containing a representative sampling of different lithographic polymers were imaged with both EUV and DUV exposures. It has been suggested by many that there is a fundamental inverse relationship between resist sensitivity and LER that leads to a fundamental limit to resist performance. It was found that no simple relationship exists between intrinsic material roughness (IMR) and sensitivity and instead some other, more complex relationship between the material prop...

Direct patterning of spin-on glass with 157nm lithography: Application to nanoscale crystal growth

Selective area homoepitaxial growth of InP in 50nm scale dense features has been demonstrated using hydrogen silsesquioxane (HSQ) as the growth mask. The HSQ growth mask was patterned lithographically using high resolution interference lithography at 157nm. Lithographic process conditions were optimized, including postapplication bake temperature, developer normality, and oxygen levels during exposure.

Dry etching of amorphous-Si gates for deep sub-100 nm silicon-on-insulator complementary metal–oxide semiconductor

Sub-100 nm gates are fabricated for fully depleted silicon-on-insulator complementary metal–oxide semiconductor transistor and circuit fabrication using optical lithography and a high density, transformer coupled plasma etch process. The antireflective coating (ARC) bake temperature and HBr/Cl2/O2 organic ARC etch chemistry were optimized to maintain device critical dimension. The amorphous silicon (a-Si) main etch uses HBr/Cl2/He/O2 and was optimized at a high HBr concentration, high temperature, low O2 concentration, and a low pressure to obtain minimal CD bias and maximum selectivity to both oxide and resist. Main Etch end-point determination was developed to trigger on a rising Cl2 reactant optical emission signature at 510 nm avoiding interference from CO lines at typical end-point determination wavelengths for integration using resist masks with a high percentage of resist area. Transistors were fabricated with gate lengths of 25 and 50 nm.

Application of chromeless phase-shift masks to sub-100-nm SOI CMOS transistor fabrication

This work looks at the application of chromeless phase-shift masks to sub-100 nm gatelength SOI transistor fabrication. The double-exposure technique of Numerical Technologies is extended to the chromeless-edge case. Two masks are used in this method. The first is a darkfield mask with chromeless edges defining the minimum geometry gates and the second is a binary blockout mask which also patterns the larger gate features. This approach provides considerably enhanced resolution performance compared with alternating aperture while still preserving good process latitudes. The chromeless mask fabrication approach is discussed. A simple, single step dry etch is used with no minimum geometry features, thus simplifying mask fabrication. We employed an 0.6 NA, DUV tool for this work together with commercially available resist and anti-reflection layers. Lithography results for k1 factors down to 0.10 and 0.3 are presented. This corresponds to CDs of 40 nm and 125 nm on our Canon EX-4, 248nm stepper. Excellent pattern transfer into polysilicon was achieved using a high density plasma etch process producing gate features down to 25 nm linewidths. We discuss the application of this method to the fabrication of sub-100 nm gate-length fully-depleted SOI CMOS transistors. We have fabricated SOI CMOS transistors with excellent short channel behavior down to 50 nm physical gate lengths. This method enables the development of deep sub-100 nm gate length CMOS technologies using standard 248- nm exposure sources.

How practical is 193 nm lithography

The use of 193 nm ArF lasers to extend optical projection lithography to its limits was proposed as early as the mid 1980s. Since then steady progress has been made in this area, and the last two years in particular have witnessed an exponentially growing interest in and commitment to its development. At present, 193 nm lithography is a leading candidate for printing 0.18 and 0.13 μm devices. This article reviews the state of development of this technology at Lincoln Laboratory. Significant progress has been made in most areas: qualification of optical materials, characterization of a prototype large‐field projection system, development of photoresist processes, and the fabrication of complementary metal‐oxide semiconductor devices.

Metrology methods for quantifying edge roughness: II

Advanced scanning electron and atomic force microscopy technique have been developed to quantify line-edge and sidewall roughness in patterned resist and silicon feature with nanometer scale accuracy. Both techniques are able to follow small changes in the line-edge roughness. The measurement repeatability of the scanning electron and atomic force microscope was characterized and is 0.1 and 0.6 nm, respectively. Any roughness measured in the single layer resist mask transfers to the underlying silicon throughout a range of pattern transfer conditions. Within the measurement precision, silicon pattern transfer does not appear to decrease or increase the sidewall or line-edge roughness. An attempt to quantify the edge-roughness spatial frequency is discussed. The scanning electron microscope is still recommended over the atomic force microscope for line-edge roughness measurements based on sample throughput.