Michael Fritze

High-speed Schottky-barrier pMOSFET with f/sub T/=280 GHz

High-speed results on sub-30-nm gate length pMOSFETs with platinum silicide Schottky-barrier source and drain are reported. With inherently low series resistance and high drive current, these deeply scaled transistors are promising for high-speed analog applications. The fabrication process simplicity is compelling with no implants required. A sub-30-nm gate length pMOSFET exhibited a cutoff frequency of 280 GHz, which is the highest reported to date for a silicon MOS transistor. Off-state leakage current can be easily controlled by augmenting the Schottky barrier height with an optional blanket As implant. Using this approach, good digital performance was also demonstrated.

High-frequency characterization of sub-0.25-/spl mu/m fully depleted silicon-on-insulator MOSFETs

A cutoff frequency, f/sub T/, of 85 GHz was measured on a fully-depleted silicon-on-insulator (FDSOI) n-MOSFET with a gate length of 0.15 /spl mu/m. The p-MOSFET with 0.22-/spl mu/m gate length has an f/sub T/ of 42 GHz. The high-frequency equivalent circuits were derived from scattering parameters for MOSFETs with various gate lengths. The effects of gate length and other device parameters on the performance of FDSOI MOSFETs at RF are discussed.

Dense only phase shift template lithography

The steady move towards feature sizes ever deeper in the subwavelength regime has necessitated the increased use of aggressive resolution enhancement techniques (RET) in optical lithography. The use of ever more complex RET methods including strong phase shift masks and complex OPC has led to an alarming increase in the cost of photomasks, which cannot be amortized by many types of semiconductor applications. This paper reviews an alternative RET approach, dense template phase shift lithography, that can substantially reduce the cost of optical RET. The use of simple dense grating templates can also eliminate serious problems encountered in subwavelength lithography including optical proximity and spatial frequency effects. We show that, despite additional design rule restrictions and the use of multiple exposures per critical level, this type of lithography approach can make economic sense depending on the number of wafers produced per critical photomask.

High-throughput hybrid optical maskless lithography: all-optical 32-nm node imaging

We analyze the performance and process latitudes of a high-throughput, all-optical lithography method that addresses the requirements of the 32-nm node. This hybrid scheme involves a double exposure and only a single photomask. The first exposure forms dense gratings using maskless immersion interference lithography. These regular grating patterns are then trimmed in a second exposure with conventional projection lithography. While the highest resolution features are formed with interference imaging, the trimming operation requires significantly lower resolution. We have performed lithography simulations examining a number of representative 32-nm node patterns; both one-dimensional and two-dimensional. The results indicate that 32-nm node lithography requirements can be met using a hybrid optical maskless (HOMA) approach. Trim photomasks can be two to three generations behind the fine features, while the trim projection tools can be one to two generations behind the fine features. This hybrid optical maskless method has many of the benefits of maskless lithography without the severe throughput challenge of currently proposed maskless technologies.

Investigation of the physical and practical limits of dense-only phase shift lithography for circuit feature definition

The rise of low-k 1 optical lithography in integrated circuit manufacturing has introduced new questions concerning the physical and practical limits of particular subwavelength resolution-enhanced im- aging approaches. For a given application, trade-offs between mask complexity, design cycle time, process latitude and process throughput must be well understood. It has recently been shown that a dense-only phase shifting mask (PSM) approach can be applied to technology nodes approaching the physical limits of strong PSM with no proximity effects. Such an approach offers the benefits of reduced mask complex- ity and design cycle time, at the expense of decreased process through- put and limited design flexibility. In particular, dense-only methods offer k 1,0.3, thus enabling 90 nm node lithography with high-numerical ap- erture 248 nm exposure systems. We present the results of experiments, simulations, and analysis designed to explore the trade-offs inherent in dense-only phase shift lithography. Gate and contact patterns corre- sponding to various fully scaled circuits are presented, and the relation- ship between process complexity and design latitude is discussed. Par- ticular attention is given to approaches for obtaining gate features in both the horizontal and vertical orientation. Since semiconductor investment is dependent on cost amortization, the applicability of these methods is also considered in terms of production volume.

Characterization of Quartz Etched PSM Masks for KrF Lithography at the 100 nm node

The application of strong phase shift masks (PSMs) such as AAPSM and Chromeless using KrF 248-nm lithography is increasingly in demand for production of advanced devices at the 130 nm node and below. Implementation of dual exposure PSM technology is becoming widely accepted as a method to achieve sub-wavelength gate and contact layer resolution for microprocessors, DRAM and thin film heads. This requires a stable and repeatable phase-shift mask process that will perform for the wafer lithographer and is manufacturable using todays leading edge photomask fabrication methods. The focus of this study is the characterization of the photomask quartz etch process. The effect of the photomasks phase depth control and the quartz etch CD control will be examined. A comprehensive mask metrology study will be supplemented by lithography process latitude data, both simulation and experimentally based. The effect of fabricating the photomask quartz trenches using either resist or chrome defined etch masks will also be studied as well as the impact on lithography process latitude. A key goal of this study is the determination of a realistic specification for the quartz etch process required for leading- edge phase-shift photomasks.

Fabrication of self-aligned 90-nm fully depleted SOI CMOS SLOTFETs

We have developed a novel sub-100-nm fully depleted silicon-on-insulator (SOI) CMOS fabrication process, in which conventional 248-nm optical lithography and nitride spacer technology are used to define slots in a sacrificial layer (SLOTFET process). This process features a locally thinned SOI channel with raised source-drain regions, and a low-resistance T-shaped poly-Si gate; Both n- and p-channel MOSFETs with 90-nm gate length have been demonstrated. At a 0.5 V bias voltage, ring-oscillator propagation delay of less than 50 ps per stage has been measured.

Application of chromeless phase-shift masks to sub-100-nm SOI CMOS transistor fabrication

This work looks at the application of chromeless phase-shift masks to sub-100 nm gatelength SOI transistor fabrication. The double-exposure technique of Numerical Technologies is extended to the chromeless-edge case. Two masks are used in this method. The first is a darkfield mask with chromeless edges defining the minimum geometry gates and the second is a binary blockout mask which also patterns the larger gate features. This approach provides considerably enhanced resolution performance compared with alternating aperture while still preserving good process latitudes. The chromeless mask fabrication approach is discussed. A simple, single step dry etch is used with no minimum geometry features, thus simplifying mask fabrication. We employed an 0.6 NA, DUV tool for this work together with commercially available resist and anti-reflection layers. Lithography results for k1 factors down to 0.10 and 0.3 are presented. This corresponds to CDs of 40 nm and 125 nm on our Canon EX-4, 248nm stepper. Excellent pattern transfer into polysilicon was achieved using a high density plasma etch process producing gate features down to 25 nm linewidths. We discuss the application of this method to the fabrication of sub-100 nm gate-length fully-depleted SOI CMOS transistors. We have fabricated SOI CMOS transistors with excellent short channel behavior down to 50 nm physical gate lengths. This method enables the development of deep sub-100 nm gate length CMOS technologies using standard 248- nm exposure sources.

Performance of excimer lasers as light sources for 193-nm lithography

The performance of argon fluoride excimer lasers is an important issue in determining the practical feasibility of 193-nm exposure systems. This paper presents a summary of the experience gained at MIT Lincoln Laboratory regarding the long-term performance of 193-nm lasers, used under conditions similar to those expected in production-type lithographic systems.

Limits of strong phase-shift patterning for device research

Advanced transistor research requires the patterning of isolated gate feature sizes well below available illumination wavelengths. In this work, we explore the limits of imaging isolated line features using double exposure strong phase shift methods and 248 nm illumination. Fundamental issues such as aerial image size,flare, simple OPC and resist aspect ratio will be addressed. Non-lithographic feature slimming methods such as UV-bake, etch biasing and oxidation will we explored as well. It is desirable that feature slimming processing also reduce line-edge roughness. Using a combination of strong PSM imaging and feature slimming, we have developed processes for the fabrication of sub-25 nm gate features required by our Schottky Barrier transistor device development efforts.