Sven Henrichs

Second level exposure for phase shift mask applications using an SLM-based DUV mask writer

Phase shift mask (PSM) applications are becoming essential for addressing the lithography requirements of the 65 nm technology node and beyond. Many mask writer properties must be under control to expose the second level of advanced PSM: second level alignment system accuracy, resolution, pattern fidelity, critical dimension (CD) uniformity and registration. Optical mask writers have the advantage of process simplicity for this application, as they do not require a discharge layer. This paper discusses how the mask writer properties affect the error budget for printing the second level. A deep ultraviolet (DUV) mask writer with a spatial light modulator (SLM) is used in the experimental part of the paper. Partially coherent imaging optics at the 248 nm wavelength provide improved resolution over previous systems, and pattern fidelity is optimized by a real-time corner enhancement function. Lithographic performance is compared to the requirements for second level exposure of advanced PSM. The results indicate sufficient capability and stability for 2nd level alternating PSM patterning at the 65 nm and 45 nm nodes.

Alternating phase shift mask technology for 65nm logic applications

Alternating Phase Shift Mask (APSM) Technology has been developed and successfully implemented for the poly gate of 65nm node Logic application at Intel. This paper discusses the optimization of the mask design rules and fabrication process in order to enable high volume manufacturability. Intels APSM technology is based on a dual sided trenched architecture. To meet the stringent OPC requirements associated with patterning of narrow gates required for the 65nm node, Chrome width between the Zero and Pi aperture need to be minimized. Additionally, APSM lithography has an inherently low MEEF that furthermore, drives a narrower Chrome line as compared to the Binary approach. The double sided trenched structure with narrow Chrome lines are mechanically vulnerable and prone to damage when exposed to conventional mask processing steps. Therefore, new processing approaches were developed to minimize the damage to the patterned mask features. For example, cleaning processes were optimized to minimize Chrome & quartz damage while retaining the cleaning effectiveness. In addition, mask design rules were developed which ensured manufacturability. The narrow Chrome regions between the zero and Pi apertures severely restrict the tolerance for the placement of the second level resists edges with respect to the first level. UV Laser Writer based resist patterning capability, capable of providing the required Overlay tolerance, was developed, An AIMS based methodology was used to optimize the undercut and minimize the aerial image CD difference between the Zero and Pi apertures.

Design for manufacturing approach to second level alternating phase shift mask patterning

A significant barrier to implementing APSM in volume production has been the expense of the mask. The cost of the mask is driven partially by the complexity of the two layer process flow required to make the mask. Typically, the 2nd level pattern is generated by upsizing the first level pattern of the pi apertures by a small amount in order to provide some overlay margin. The amount of upsizing is limited by the smallest chrome feature present in the pattern. The overlay margin between the first and 2nd level patterns can be improved by sizing the 2nd level more on larger chrome structures, when present. With a simple set of rules, it is possible to generate a 2nd level pattern with greater than ten times reduction in the number of corners, as measured by the number of vertices in the pattern, and minimize the number of marginal patterns in the design. This also has the beneficial side effect of significantly reducing the file size of the 2nd level pattern which can reduce the write time on some writers. Existing design rules can be exploited or additional rules imposed that can further improve the capability of the 2nd level APSM process. The right set of mask design rules can enable the use of lower fidelity writer for 2nd level patterning which can significantly reduce cost. The improved margin can increase yield and may even enable a less capable/expensive patterning tool to be used for 2nd level patterning.

Optical DC overlay measurement in the 2nd level process of 65 nm Alternating Phase Shift Mask

Alternating phase shift mask (APSM) techniques help bridge the significant gap between the lithography wavelength and the patterning of minimum features, specifically, the poly line of 35 nm gate length (1x) in Intels 65 nm technology. One of key steps in making APSM mask is to pattern to within the design tolerances the 2nd level resist so that the zero-phase apertures will be protected by the resist and the pi-phase apertures will be wide open for quartz etch. The ability to align the 2nd level to the 1st level binary pattern, i.e. the 2nd level overlay capability is very important, so is the capability of measuring the overlay accurately. Poor overlay could cause so-called the encroachment after quartz etch, producing undesired quartz bumps in the pi-apertures or quartz pits in the zero-apertures. In this paper, a simple, low-cost optical setup for the 2nd level DC (develop check) overlay measurements in the high volume manufacturing (HVM) of APSM masks is presented. By removing systematic errors in overlay associated with TIS and MIS (tool-induced shift and Mask-process induced shift), it is shown that this setup is capable of supporting the measurement of DC overlay with a tolerance as small as +/- 25 nm. The outstanding issues, such as DC overlay error component analysis, DC - FC (final check) overlay correlation and the overlay linearity (periphery vs. indie), are discussed.