Kishore K. Chakravorty

Alternating phase shift mask architecture scalability, implementations, and applications for 90-nm and 65-nm technology nodes and beyond

Alternating phase shift mask (altPSM) as a strong resolution enhancement technique is increasingly required to meet the tighter lithographic requirements on gate critical dimension (CD) control, depth of focus and low k1 applications in full chip patterning of logic and memory devices. While the frequency doubling mechanism of altPSM benefits the quality of imaging, the inherent intensity asymmetry between phase shifters, or image imbalance, causes line shift. The effect of mask topography on electromagnetic wave propagation must be compensated in practice. Various designs of mask structure for correcting the intrinsic imaging asymmetry have been extensively studied. In this paper, we discuss several image imbalance correction methods for hidden phase edge altPSM architectures, including chrome undercut, shifter width sizing, sidewall chrome alternating aperture mask. We compared both hidden phase edge as well as exposed phase edge altPSM in terms of scalability, image correction effectiveness, and manufacturability for 90-nm, 65-nm technology nodes and beyond. Specifically, we define the altPSM architecture scalability in terms of three key components: 1. Mask manufacturability, design layout complexity, and effectiveness of image balance correction, 2. Mask patterning resolution, pattern fidelity, image placement, CD & overlay control at both chrome and glass levels, 3. Tightening quartz etch process control for given phase error tolerance. Applications of altPSM technology to line/space, hole, and phase shifted assisted features patterning with various altPSM architectures are also addressed.

EUV mask infrastructure readiness and gaps for TD and HVM

The industry is transitioning EUV lithography from feasibility phase to technology development. EUV mask infrastructure needs to be prepared to support the technology development and ready to enable the implementation of EUV lithography for production. In this paper, we review the current status and assess the readiness of key infrastructure modules in EUV mask fabrication, inspection and control, and usage in a mask cycle: blank quality and inspection, pattern inspection, defect disposition and repair, pellicle integration, and handling of pelliclized masks.

Alternating phase shift mask technology for 65nm logic applications

Alternating Phase Shift Mask (APSM) Technology has been developed and successfully implemented for the poly gate of 65nm node Logic application at Intel. This paper discusses the optimization of the mask design rules and fabrication process in order to enable high volume manufacturability. Intels APSM technology is based on a dual sided trenched architecture. To meet the stringent OPC requirements associated with patterning of narrow gates required for the 65nm node, Chrome width between the Zero and Pi aperture need to be minimized. Additionally, APSM lithography has an inherently low MEEF that furthermore, drives a narrower Chrome line as compared to the Binary approach. The double sided trenched structure with narrow Chrome lines are mechanically vulnerable and prone to damage when exposed to conventional mask processing steps. Therefore, new processing approaches were developed to minimize the damage to the patterned mask features. For example, cleaning processes were optimized to minimize Chrome & quartz damage while retaining the cleaning effectiveness. In addition, mask design rules were developed which ensured manufacturability. The narrow Chrome regions between the zero and Pi apertures severely restrict the tolerance for the placement of the second level resists edges with respect to the first level. UV Laser Writer based resist patterning capability, capable of providing the required Overlay tolerance, was developed, An AIMS based methodology was used to optimize the undercut and minimize the aerial image CD difference between the Zero and Pi apertures.

Optical DC overlay measurement in the 2nd level process of 65 nm Alternating Phase Shift Mask

Alternating phase shift mask (APSM) techniques help bridge the significant gap between the lithography wavelength and the patterning of minimum features, specifically, the poly line of 35 nm gate length (1x) in Intels 65 nm technology. One of key steps in making APSM mask is to pattern to within the design tolerances the 2nd level resist so that the zero-phase apertures will be protected by the resist and the pi-phase apertures will be wide open for quartz etch. The ability to align the 2nd level to the 1st level binary pattern, i.e. the 2nd level overlay capability is very important, so is the capability of measuring the overlay accurately. Poor overlay could cause so-called the encroachment after quartz etch, producing undesired quartz bumps in the pi-apertures or quartz pits in the zero-apertures. In this paper, a simple, low-cost optical setup for the 2nd level DC (develop check) overlay measurements in the high volume manufacturing (HVM) of APSM masks is presented. By removing systematic errors in overlay associated with TIS and MIS (tool-induced shift and Mask-process induced shift), it is shown that this setup is capable of supporting the measurement of DC overlay with a tolerance as small as +/- 25 nm. The outstanding issues, such as DC overlay error component analysis, DC - FC (final check) overlay correlation and the overlay linearity (periphery vs. indie), are discussed.