Ekkehard Meusel

Characterization of self-heating in advanced VLSI interconnect lines based on thermal finite element simulation

In this paper, self-heating of interconnects has been shown to affect the lifetime of next generation integrated circuits significantly more severely than todays. The paper proves the necessity for extending the system of design rules, proposes a thermal design rule, and presents an efficient and quantitatively accurate thermal simulator as tool for the design process.

Microstructural dependence of constitutive properties of eutectic SnAg and SnAgCu solders

The paper presents constitutive models for eutectic SnAg and SnAgCu solders. Experimental investigations were carried out on specimens of different microstructures. The three specimen types have been flip chip solder joints, pin trough hole solder joints and standard hulk solder specimens. The bulk solder specimen was a dog-hone type specimen (diameter = 3 mm, length = I17 mm). The pin trough hole solder joint consisted on a copper wire that was soldered into a hole of a double sided printed circuit board (thickness I .5 mm, solder gap 0.1 mm). The flip chip solder joint specimen consisted of two silicon chips which were connected by 4 flip chip joints (one on each comer). Flip chip bumps (footprint 200 pm x 200 pm, joint height 165 ... 200 pm) were created by printing solder paste. Constant-load creep tests were carried out on all three specimen types at temperatures between 5 “C and 70 “C. Creep data was taken for strain rates between IO-’’ SKI and IO” s-I. The specimens were tested in “as cast” condition and after thermal storage. Beside the creep behaviour of the solders, the time independent elastic plastic behaviour was determined. Strain-stress-curves were recorded from the “flip chip solder joint” specimens, using a micro shear tester. The microstructural properties of the bulk specimens and real solder joints were examined using metallographic sectioning, optical microscopy techniques, and SEMmicroprobe analysis. The results of the microstructural analysis were related to the investigated mechanical properties of the solders. Models of SnAg3.5 and SnAg4CuO.5, that can he used with the ANSYSTM FEM software package, will he presented.

Time-dependent material modeling for finite element analyses of flip chips

Finite element analysis (FEA) has been established as an effective method for reliability assessment of flip chip assemblies. The simulation results are significantly dependent on the selected material models. Regarding flip chip assemblies, this statement mainly applies to the tin lead solder of the flip chip joints and the encapsulant-the so-called underfill. Comprehensive material data of eutectic solder were determined on real flip chip joints. Based on these data, three modeling approaches were evaluated (target platform was the FEA code ANSYS): viscoplasticity (Anands model), power law creep (with 2 terms)+plasticity, and sinh law creep+plasticity (as user defined model in ANSYS). Underfills are often modeled as very simple elastic materials. Tensile tests were performed on underfill samples to study its real behavior. Two modeling approaches of a representative underfill were evaluated: linear elasticity and linear viscoelasticity. The properties of all above mentioned approaches are discussed in terms the simulated material behavior at various temperatures and deformation rates. For each combination of approaches, temperature cycling tests on a flip chip module were simulated by ANSYS. Different combinations of modeling approaches for solder and underfill led to different simulation results although each model was based on the same measurement data. The differences are discussed and conclusions are drawn about which modeling approach is preferable for typical applications.

Creep and crack propagation in flip chip SnPb37 solder joints

The lifetime determining event in flip chip packages is the fracture of solder joints. Crack initiation and crack growth in micro solder joints, however, are supposed to differ very much from that of bulky samples of steel, nickel, copper etc. that are usually used in fracture mechanics tests. Hence, the commonly known fracture laws do not hold for FC joints while alternative laws have not been established yet because of a lack of experimental data. The paper presents the results of reversible shear tests on flip chip solder joints under isothermal conditions. Two micro shear testers have been designed and built for this task. One tester is optimized to achieve high precision. In contrast to similar setups, this tester is actively compensated for its finite stiffness. Therefore, it is able to record force displacement hysteresis with a resolution of better than 1 mN and 20 nm force and displacement measurements, respectively. The second tester works very similar but fits in a UHV chamber. In this way, it enables in-situ SEM observations during the test. The results of this study show that the deformation behavior of flip chip solder joints to be more alike to that of bulk samples with a comparable micro structure than it is commonly believed based on published data. The parameters of the determined creep equation indicating what deformation mechanism dominates at what strain rate. The results of the creep tests are compared with that of crack growth experiments. The influence of different deformation mechanisms on the crack growth rate is discussed.

Time-independent plastic behaviour of solders and its effect on FEM simulations for electronics packages

The time-independent behaviour of SnPb37, SnAg3.5 and SnAg4Cu0.5 has been investigated on flip chip solder joints. The test specimen consisted of two silicon chips (3.3 mm in square) bonded by 4 flip chip joints (one at each corner). The Dresden University Micro Shear Tester has been used for the experiments with this type of specimen. In contrast to similar set-ups, it is actively compensated for its finite stiffness. Therefore, it is able to record force displacement hysteresis with a resolution of better than 1 mN and 20 nm, respectively. Based on these measurements, the parameters of the constitutive equations have been evaluated by FEM analysis. This way, the complex stress state within the sample during the test has been considered precisely providing for high accuracy of the parameter extracted. As a typical application, a three point bending experiment has been simulated by FEM applying different constitutive models for the solder material. Comparing the results, it becomes clear: All the three ingredients, i.e., the elastic, the creep, and the time-independent plastic data, are required in the model. Otherwise it would be incomplete and hence insufficient for assisting in the design of todays electronics packages even with respect to the most frequent load cases.

Polypyrrole as an interlayer for bonding conductive adhesives to activated aluminum bond pads

Polymeric electronic packaging using conductive adhesives has been identified as a key technology for future assembly and manufacturing. This paper presents a study on process development for conductive adhesives as solder replacement. The main objective investigated is the use of intrinsic conductive polymers directly bonded to bond pads as a low cost effective procedure. The process consists of a technology for the chemical deposition of polypyrrole as an interlayer on aluminum bond pads including the activation of the aluminum surface and the deposition of an isotropic conductive adhesive. Results regarding the chemical characterization of the conductive interlayer by energy disperse analysis of X-ray Spectroscopy and the physical properties of the bumps consisting of a commercially used isotropic conductive adhesive are presented. The paper emphasizes electrical measurements, i.e., contact resistance and the shear strength of the bumps to the bond pads. The approach and analyses described, as well as the practical conclusions for the optimal fabrication of the conductive interlayer for the deposition of adhesives, are an important step forward in low cost procedures in the field of micro packaging.

Fracture behaviour of flip chip solder joints

The paper presents the results of isothermal cyclic shear experiments on flip chip solder joints. Two micro shear testers have been designed and built for this task. One tester is optimised to achieve high precision. Since it is actively compensated for its finite stiffness, this tester is able to record force displacement hysteresis with a resolution of better than 1 mN and 20 nm force and displacement measurements, respectively. The second tester works very similar but fits in a UHV chamber. This way, it enables in-situ SEM observations during the test. The experiments were done exactly the same way with both machines. The experimental program consisted on two types of isothermal experiments. The first type used a cyclic triangular strain wave with constant frequency but different amplitudes as the load function. The second type used a cyclic triangular strain wave with constant amplitude but different frequencies as the load function. The strain wave amplitudes ranged from /spl Delta//spl epsi/=0.3%...4%, the strain wave frequencies ranged from f=0,0004 Hz ... 10 Hz. The test temperature was 300 K. The investigated solder materials have been Sn63Pb37 and Sn95.5Ag4Cu0.5. In order to model crack propagation in FEM simulations, two different criteria have been tested, to develop a simple crack propagation model. The first criterion was plastic strain energy /spl Delta/W/sub pl/ and the second criterion was accumulated inelastic strain /spl epsi//sub acc/. The paper gives crack propagation relations for both criteria.

Mechanism and growth rate of underfill delaminations in flip chips

Delamination of underfill in flip chips is a widely accepted major cause for failure. However, there is a lack of information on the mechanism of this effect. A novel methodology is used to examine these delaminations in this paper. Instead of the expensive and time-consuming scanning acoustic microscopy with limited resolution, an optical method is established. For that the silicon chip was replaced by a glass chip (Pyrex). With usual passivations, the component is comparable to silicon flip chips from the mechanical point of view. This gives the possibility to look at the interface underfill/passivation or underfill/PCB by a microscope and a CCD camera. Photo analysis software allows to quantify delaminated versus not delaminated regions. Hence, an evaluational method for material and geometric impacts to delaminations is available. The effect of the following parameters were observed: chip size, bump height, substrate thickness; passivation, underfill material; flux material, die sites with and without solder resist. Beside other results, it has been shown, that the most reliable combination was made of 0.8 mm substrate, a passivation of SiO/sub 2/ and no use of solder resist. A good meniscus could improve the hydro-thermal fatigue. As a function of geometric parameters different behavior of crack growth were found.

Conductive polymers for microelectronic packaging: chip bonding to polymer films †

A novel flipchip-like microelectronic packaging technology for bonding integrated circuits to polymer foils using laser micromachining technique and a wet chemical metallization process of conductive polymers has been developed. This paper will focus on the deposition of polypyrrole onto the aluminum surface and the characterization of the thin film using scanning electron microscopy, auger electron spectroscopy and X-ray photoelectron spectroscopy. The conductive polymer is metallized by copper electroplating for connecting the integrated circuit to the polyimide foil. Electrical measurements were performed on patterned substrates with a layer system consisting of polypyrrole/copper/tin–lead deposited on aluminum bond pads. The characteristic current/voltage curve shows an ohmic contact behavior which is of fundamental importance for the development of chip bonding technology using conductive polymers.

A cost-effective assembly process for flip chips on FR-4

The application of flip chips is an attractive approach for many innovative products-especially portable systems. For cost reasons, the flip chip assembly has to be integrated into the existing surface mount technology. In this work, the main aspects of an SMT compatible assembly process for flip chips on FR-4 were studied. Test chips up to 9.6 mm edge length were mounted. Two types of substrates were used successfully: FR-4 with SIPAD solder deposits and FR-4 with modified solder mask patterns. The bumping process of the chips as well as the layout of the chips and the substrates is introduced. The placement and the reflow soldering were performed with regular equipment. Important issues of the soldering and the flux selection are discussed. Complete underfilling of the attached flip chips is necessary to achieve a sufficient reliability level. A test methodology is presented to visualize and assess the flow behavior of underfill materials. Measurement results of three representative underfills are discussed. Finally, first reliability results are introduced.