Sven Van Elshocht

AVD and MOCVD TaCN-based Films for Gate Metal Applications on High k Gate Dielectrics

After overcoming the integration issues for the last few years, the insertion of high k dielectrics and metal gate stacks are now becoming obvious into probably 45nm and surely 32nm technology node. As the devices are scaled down, metal gate technology in conjunction with high-k gate dielectric are critical to replace conventional nitrided-oxide/poly-Si gate stacks. Advanced CMOS requires compatibility for a single or dual metal gate process with suitable work-functions to have the right Vt for nMOS and pMOS respectively. Obtaining pMOS solutions has been a challenge to meet band-edge work-function of >5.2eV.

Atomic Layer Deposition of HfO2 on (100) and (110) Oriented Silicon Surfaces

The continuous need for enhanced performance of the integrated circuits demands for the development of new device structures other than the conventional planar MOSFET. Multi-gate transistors – such as the FinFET – are considered to overcome the technological challenges as they can be scaled down to very short gate lengths. Furthermore, scaling of the device dimensions requires the introduction of gate dielectrics with a permittivity κ, higher than that of SiO2. As the FinFET consists of a vertical silicon fin, the high-κ dielectric has to be deposited on silicon with both a (100) and (110) crystal orientation. Moreover, this substrate topology requires the use of a deposition technique that offers excellent conformality and step coverage of the as-grown material. These characteristics are ensured by using Atomic Layer Deposition (ALD) to grow the gate dielectric.

Scaling Down of MOCVD HfSiON to 1nm EOT

High dielectric constant (high-k) dielectrics, such as hafnium oxide, zirconium oxide, alumina and their silicates, were suggested materials for CMOS scaling [1]. Among these HiK materials, Hf-silicate (HfSiON) is considered as a promising candidate because of its high thermal stability and compatibility with Fully Silicided gate electrode (FUSI). Metal-organic chemical vapor deposition (MOCVD) has been proven a reliable process to deposit HfSiOx layers [2]. In this paper we demonstrate that MOCVD HfSiON gate dielectric can be scaled down to 1nm EOT with a controlled gate leakage < 1A/cm in FUSI/HfSiON CMOS devices.

Alternative Gate Dielectric Materials

S. Van Elshocht, A. Hardy, S. De Gendt, C. Adelmann, D. Brunco, M. Caymax, T. Conard, P. Delugas, P. Lehnen, D. Shamiryan, R. Vos, T. Witters, P. Zimmerman, M. Meuris, and M. Heyns 1 IMEC vzw, Kapeldreef 75, B-3001 Heverlee, Belgium 2 University of Hasselt, Inorganic and Phys. Chemistry, Agoralaan, gebouw D B-3590 Diepenbeek, Belgium 3 University of Leuven, Department of Chemistry, Celestijnenlaan 200F, B-3001 Heverlee, Belgium 4 AIXTRON, Kackertstr. 15-17, Aachen, Germany

Replacing SiO2 - Material and processing aspects of new dielectrics

To increase CMOS performance, new materials are continuously being introduced. For logic technologies, high-k dielectrics and metal gates have been engineered successfully (1). Yet, new challenges are underway, as these high-k materials are considered as enabling technologies for advanced channel materials such as Ge and III-V materials. Also for future memory technologies, novel dielectric materials, with challenging CET/leakage specifications are required. Additionally, both for memory (trench capacitors) and logic (3D transistors), additional challenges are imposed on these materials, as suitable step coverage of the dielectric deposition processes is required (2). The move away from conventional SiO2 based dielectrics, and thus also from the thermal oxidation processes has opened pathways for physical vapor deposition (and controlled oxidation) or chemical vapor deposition processes to conquer the market for critical dielectric deposition processes. Once optimized processes are developed, likely identical material properties can be achieved for the same dielectric deposited by means of a variety of different deposition techniques. Yet, the pathway to these optimized processes is covered with challenging features, both intrinsic to the deposition process, to the nature of the dielectric or application.