Shuja A. Abbasi

Optimized Design of a 32-nm CNFET-Based Low-Power Ultrawideband CCII

CMOS technology faces significant challenges like tunneling effect, random dopant fluctuation, and line edge roughness at channel lengths below 45 nm. Carbon nanotube-based electronics seems to be a better prospect for extending the saturating Moores law because of its higher mobility, scalability, and better channel electrostatics. This paper presents an optimum design of a wide bandwidth, high-performance carbon nanotube field-effect transistor (CNFET) realization of a dual-output second-generation current conveyor (CCII±) at a 32-nm technology node. The performance of the CCII module has been thoroughly investigated in terms of number of carbon nanotubes (CNTs), the diameter of CNT and inter-CNT pitch. The parameters of individual CNFET are then modified to further improve the performance. The performance of the optimum CNFET (ITOPT)-based CCII is then compared with CMOS at different supply voltages. It has been found that CNFET-based CCII provides excellent high-frequency response and also consumes lower power at scaled supply voltage compared with its CMOS counterpart.

A High-Performance Source Engineered Charge Plasma-Based Schottky MOSFET on SOI

In this paper, we address an important issue of low ON current in a Schottky barrier (SB) MOSFET by proposing a novel structure of Schottky MOSFET on silicon on insulator. The proposed Schottky device employs a dual material at the source side and is being named as the source engineered SB MOSFET (SE-SB-MOSFET). Erbium silicide (ErSi1.7) is used as the main source material, and Hafnium is used as a source extension. The use of Hafnium as a source extension induces an n+-type charge plasma in an undoped silicon film, which significantly reduces the SB thickness. A calibrated simulation study has shown that the ON current (ION) and ION/IOFF have increased by 225 and 65×, respectively, in the proposed device in comparison with the conventional SB-MOSFET device. The ac analysis has shown that the cutoff frequency (fT) in the proposed SE-SB-MOSFET (~200 GHz) has increased by 200× as compared with the conventional SB-MOSFET (~1 GHz). Furthermore, the performance of the proposed device has been tested at the circuit level also. It has been observed from the transient analysis that a significant reduction in switching ON delay (65×) and switching OFF delay (33%) has been achieved in the proposed SE-SB-MOSFET-based inverter in comparison with the conventional device-based inverter. Furthermore, the use of the charge plasma concept makes the fabrication of the proposed device relatively easy as it uses low thermal budget.

A high performance charge plasma PN-Schottky collector transistor on silicon-on-insulator

In this paper, we propose a new high performance PN-Schottky collector (PN-SC) lateral bipolar junction transistor (BJT) on silicon-on-insulator (SOI). The proposed device addresses the problem of poor speed of conventional lateral PNP-BJT device by using a Schottky collector. Further, it does not use the conventional ways of ion implantation/diffusion to realize n and p type doped region. However, it uses metal electrodes of different work functions to create n and p type charge plasma in an undoped silicon film. The simulation study of the proposed lateral PN-SC bipolar charge plasma transistor on SOI (PN-SC-BCPT) device has shown a significant improvement in current gain (?), cutoff frequency (f T) and switching performance in comparison to conventional PNP-BJT and PNP-bipolar charge plasma transistor (PNP-BCPT) devices. A significantly high ? is obtained in the proposed PN-SC-BCPT (?2100) in comparison to PNP-BCPT (?1450) and the conventional BJT (?9) devices, respectively. It has been observed that there is 89.56% and 153.5% increase in f T for the proposed PN-SC-BCPT device (2.18 GHz) in comparison to conventional PNP-BJT (1.15 GHz) and PNP-BCPT (0.86 GHz) devices, respectively. Further, reductions of 24.6% and 15.4% in switching ON-delay and 66% and 30.76% in switching OFF-delay have been achieved in the proposed device based inverters in comparison to PNP-BCPT and the conventional BJT devices based inverters, respectively. Furthermore, the proposed device does not face doping related issues and the requirement of high temperature processing is absent.

VLSI Architecture of Fuzzy Logic Hardware Implementation: a Review

A contributory paper on the study of VLSI architectures of various fuzzy processors and controllers designed for various applications is presented. The paper focuses on the study of VLSI implementation of fuzzy logic hardware to result in small silicon area, high speed of operation and adaptability to different application domains. This paper reviews the circuit and architecture level designing of various components of the fuzzy processors, such as, fuzzifiers, defuzzifiers, inference and rule base. A comparative analysis of the performance of these components has been performed. It is observed that there is a scope for further improvement in terms of power consumption, speed of operation, area and redundancy in these fuzzy processors. Further, from the study it is seen that the design emphasis should be more on inference engine performance and defuzzification units, because of the complexity of computations handled by them. The optimization in these units results in a significant improvement in the overall performance of the system.

An overview of advanced FPGA architectures for optimized hardware realization of computation intensive algorithms

Algorithms used in signal and image processing applications are computationally intensive. For optimized hardware realization of such algorithms with efficient utilization of available resources, an in-depth knowledge of the targeted field programmable gate array (FPGA) technology is required. This paper presents an overview of the architectures and technologies used in modern FPGAs. A case study of most popular and widely used state-of-the-art commercial FPGA technologies from Xilinx and Altera is also presented. Three-Dimensional (3D)-FPGA architecture is also discussed.

A proposed FPGA-based parallel architecture for matrix multiplication

Matrix multiplication is a computation intensive operation and plays an important role in many scientific and engineering applications. For high performance applications, this operation must be realized in hardware. This paper presents a parallel architecture for the multiplication of two matrices using field programmable gate array (FPGA). The proposed architecture employs advanced design techniques and exploits architectural features of FPGA. Results show that it provides performance improvements over previously reported hardware implementation. FPGA implementation results are presented and discussed.

A novel VLSI architecture for a fuzzy inference processor using Gaussian-shaped membership function

The widespread application of fuzzy logic in various fields has been hindered by the problem of low speed of operation of fuzzy processors. Both hardware and software approaches have been adopted to increase the speed of operation of the fuzzy processors in general and inference processing in particular. To improve the inference processing, the calculation of matching degree MD between the fuzzified input and the antecedent membership functions MF has to improve, as it needs very high latency and limits the overall inference performance. In this paper, a novel architecture of a MAX-MIN circuit, used for calculating the MD between two Gaussian-shaped MFs, used first time, has been proposed. The proposed architecture is area, power, speed efficient and flexible in comparison to existing architectures using trapezoid-MF, as the number of multiplexing and subtracting operations has been reduced. Further, based on the novel architecture of MAX-MIN calculator circuit, a novel fuzzifier, fuzzy decoder, fuzzy inferencing system and a complete fuzzy inference processor have been proposed and analyzed. The VHDL modeling and XILINX and Vertex based FPGA implementation of all proposed architectures have been performed.

A review of FPGA-based design methodology and optimization techniques for efficient hardware realization of computation intensive algorithms

Field programmable gate arrays (FPGAs) have emerged as platform of choice for efficient hardware realization of computation intensive algorithms because of their intrinsic parallelism and flexible architecture. However, to achieve high performance, FPGA must be supported by efficient design methodology and optimization techniques. In this paper, FPGA-based design methodology and optimization techniques that can be employed to obtain area, speed and power efficient circuits are reviewed and presented.

Single chip FPGA based realization of arbitrary waveform generator using rademacher and walsh functions

Arbitrary waveform generators (AWGs) are becoming increasingly important for test and measurement applications. This paper describes a new approach for generating arbitrary waveforms using FPGA and a set of Rademacher and Walsh functions. Utilizing these orthogonal functions, any periodic waveform can be realized. Recent advancements in field programmable gate array (FPGA) technology have made waveform generation very easy and cost-effective. For demonstration purpose we used a custom defined arbitrary waveform that is a concatenation of trapezoidal, sinusoidal and triangular waveforms. Simulation results for the proposed AWG are presented. Topdown approach has been adopted to realize the waveform genera in Spartan-3 FPGA. Th e maximum clock frequency for this design is 24.944 MHz with a power consumption of 62 mW

Hardware realization of Walsh functions and their applications using VHDL and reconfigurable logic

Orthogonal functions/transforms such as Rademacher functions and Walsh functions find extensive use in Scientific and Engineering applications. Software realization of such functions has been common for quite some time. However, hardware realization has distinct advantages and is now feasible and economically viable due to advancements made in the Microelectronics technology. Rademacher functions and Walsh functions have therefore been realized using high level design techniques targeted to Xilinx FPGAs. The application of these functions in generating digital and analog sinusoidal waves on the same chip has been demonstrated.