Syed Zahid Ahmed

SmartEEG: A multimodal tool for EEG signals

In this paper we present an hardware realisation for an image coder used in the SmartEEG project. This collaborative project has the aim of the conception of a multimodal tool for EEG signal to allow transmission of a complete examination of a patient. We show that we can expect good performance on a FPGA board for the time consuming part of this tool that is the image coder.

FPGA implementation of Hierarchical Enumerative Coding for locally stationary image source

In this paper we present a novel high performance, low resource utilization and power efficient hardware architecture of an entropy coding scheme. The proposed architecture implements the Hierarchical Enumerative Coding algorithm (HENUC) on an embedded soft-processor based System-on-Chip, in which HENUC is an integral part of a wavelet based encoder oriented for locally stationary image source. Though HENUC has been implemented on an embedded DSP architecture before, the throughput was low. This paper proposes an optimized parallel architecture for HENUC, which is validated on a Terasic DE4-230 board containing Altera Stratix IV FPGA. Our implementation at 100MHz provides 5.7x speedup over Intel Xeon 8-core CPU and 12.3x speedup over TI DSP for 512 × 512 image while consuming less than 500 mw FPGA core power.

FPGA vs DSP: A throughput and power efficiency comparison for Hierarchical Enumerative Coding

A comparative study of Hierarchical Enumerative Coding (HENUC) for FPGA and DSP implementation is presented. HENUC is a lossless fixed-point entropy coding algorithm employed by a wavelet-based image encoder, which provides good compression performance for the locally stationary image data. It has been implemented in our previous work on an Alteras 40nm Stratix IV EP4SGX230 FPGA as a hardware IP accelerator in a Nios II based system. In this paper, we implemented it on a Texas Instrumentss (TI) 40nm Integra C6A816x/AM389x DSP. We present experimental results regarding the execution time, resource utilization and core power consumption of the two implementations and we evaluate their throughput and power efficiency. Our results show that a highly parallelized FPGA implementation at 100MHz is 12.3× faster than a highly tuned DSP implementation running at 1.5 GHz and consumes 2.4× less power, they also show that the proposed algorithm is more suitable for hardware implementation.

Synchronizing physiological data and video in a telemedicine application: A multimedia approach

Several medical examinations require that multiple modalities of exams are stored in a synchronized manner. For instance, an EEG exam needs that several physiological signals along with video of the exam are acquired synchronously to aid the neurophysiologists to perform their diagnostics. Furthermore support for telemedicine for such exams have become important in recent years. The existing EDF standard that is used for physiological signals makes it difficult to provide integrated support of adding video and compressed component data, however due to widespread use of EDF standard in the domain, cross compatibility with EDF standard for physiological data is also essential. We present in this work a novel idea to solve these issues. Our approach uses standard multimedia containers in which physiological data are embedded alongside video and audio. This paper provides our analyses of the state of the art of multimedia containers EDF, AVI, ASF, MPEG and MKV and their potentials for a telemedicine application and outlines how MKV stands out as an interesting option in this regard, allowing also capability of compression of physiological data if needed.

High-throughput parallel DWT hardware architecture implemented on an FPGA-based platform

AbstractTo detect fast myoclonus jerks, doctors require a full-HD video capture of the patient at 100 frames per second. Real-time video compression becomes mandatory to archive/transmit the generated data. To achieve this goal, we used a certified medical imaging coder based on discrete wavelet transform (DWT). Thus, a major challenge was to design a 2D DWT architecture, achieving the throughput of 100 full-HD frames/s. The novel unified 2D DWT computation architecture performs both horizontal and vertical transform simultaneously and eliminates the problem of column-wise image pixel accesses to/from the off-chip DDR RAM. All of these factors have led to the reduction of the required off-chip DDR RAM bandwidth by more than 2X. The proposed concept uses four-port line buffers leading to pipelined parallel processing of direct memory access (DMA) read, horizontal 1D DWT, vertical 1D DWT, and DMA write. The proposed architecture has cycles per pixel of just 1/8, making it far exceeds 100 full-HD fps and well positioned for the 4K and 8K video processing. Finally, we highlighted that the developed architecture is highly scalable, outperforms state of the art and is deployed in a first video EEG medical prototype.

High frame rate medical quality video compression for tele-EEG

More and more, exams require medical images as a tool to diagnose pathologies. Thus, the transfer and storage of the exam data becomes a critical issue. To address this issue, an image compression algorithm called Waaves has been developed and certified for medical imaging. Our work in this paper deals with a scenario of EEG exams where video of the patient is also recorded in order to correctly diagnose myoclonus pathologies. To achieve this goal, the video needs to be of high quality and at frame rate of at least 100 frames per second. This high data rate cannot be compressed on the fly by Waaves codec. In this paper, we present a novel codec based on the Waaves compression algorithm that fits the requirements of tele-video-EEG. We have used the characteristics of the input sequence and the analysis of the original codec, to improve the compression speed. The proposed video codec has shown a speed-up of around 3.4 times compared to the original algorithm. In addition, we have been able to improve the compression ratio while retaining necessary quality to identify myoclonus.

Accelerating Heap-Based Priority Queue in Image Coding Application Using Parallel Index-Aware Tree Access

We present a novel heap-based priority queue structure for hardware implementation which is employed by a wavelet-based image encoder. The architecture exploits efficient use of FPGA’s on-chip dual port memories in an adaptive manner. By using 2x clock speed we created 4 memory ports along with intelligent data concatenation of parents and children queue elements, as well as an index-aware system linked to each key in the queue. These innovations yielded in cost effective enhanced memory access. The memory ports are adaptively assigned to different units during different computation phases of operations in a manner to optimally take advantage of memory access required by that phase. We designed this architecture to incorporate in our Adaptive Scanning of Wavelet Data (ASWD) module which reorganizes the wavelet coefficients into locally stationary sequences for a wavelet-based image encoder. We validated the hardware on an Altera’s Stratix IV FPGA as an IP accelerator in a Nios II processor based System on Chip. The architectural innovations can also be exploited in other applications that require efficient hardware implementations of priority queue. We show that our architecture at 150MHz can provide 45X speedup compared to an embedded ARM Cortex-A9 processor at 666MHz.