T. Hemperek

DEPFET Active Pixel Detectors for a Future Linear

The DEPFET collaboration develops highly granular, ultra-transparent active pixel detectors for high-performance vertex reconstruction at future collider experiments. The characterization of detector prototypes has proven that the key principle, the integration of a first amplification stage in a detector-grade sensor material, can provide a comfortable signal to noise ratio of over 40 for a sensor thickness of 50-75 μm. ASICs have been designed and produced to operate a DEPFET pixel detector with the required read-out speed. A complete detector concept is being developed, including solutions for mechanical support, cooling, and services. In this paper, the status of the DEPFET R & D project is reviewed in the light of the requirements of the vertex detector at a future linear e+e- collider.

e^{+}e^{-}

Monolithic Active Pixel Sensors (MAPS) have been developed since the late 1990s based on silicon substrates with a thin epitaxial layer (thickness of 10–15 μm) in which charge is collected on an electrode, albeit by disordered and slow diffusion rather than by drift in a directed electric field. As a consequence, the signal of these conventional MAPS is small (≈1000 e−) and the radiation tolerance is limited. In this paper, the development of a fully Depleted Monolithic Active Pixel Sensors (DMAPS) based on a high resistivity substrate allowing the creation of a fully depleted detection volume is presented. This concept overcomes the inherent limitations of charge collection by diffusion in the standard MAPS designs. We present results from a prototype chip EPCB01 designed in a commercial 150 nm CMOS technology. The technology provides a thin (≈50 μm) high resistivity n-type silicon substrate as well as an additional deep p-well which allows to integrate full CMOS circuitry inside the pixel. Different matrix types with several variants of collection electrodes and pixel electronics have been implemented. Measurements of the analog performance of this first implementation of DMAPS pixels are presented.

Collider

New monolithic pixel detectors integrating CMOS electronics and sensor on the same silicon substrate are currently explored for particle tracking in future HEP experiments, most notably at the LHC . The innovative concept of Depleted Monolithic Active Pixel Sensors (DMAPS) is based on high resistive silicon bulk material enabling full substrate depletion and the application of an electrical drift field for fast charge collection, while retaining full CMOS capability for the electronics. The technology (150 nm) used offers quadruple wells and allows to implement the pixel electronics with independently isolated N- and PMOS transistors. Results of initial studies on the charge collection and sensor performance are presented.

DMAPS: a fully depleted monolithic active pixel sensor—analog performance characterization

In the new Belle II detector, which is currently under construction at the SuperKEKB accelerator, a two layer pixel detector will be introduced to improve the vertex reconstruction in a ultra high luminosity environment. The pixel detector will be produced using the DEPFET technology. A new ASIC (Data Handling Processor or DHP) designed to steer the readout process, pre-process and compress the raw data has been developed. The DHP will be directly bump bonded to the balcony of the all-silicon DEPFET module. The current chip prototype has been produced in CMOS 90 nm. Its test results, including the data processing quality, the signal integrity of the gigabit transmission lines will be presented here. For the final chip, which will be produced using CMOS 65 nm, single event upset (SEU) cross sections were measured. An additional chip, containing memory blocks to be tested, was submitted and produced using this technology.

Characterization of a Depleted Monolithic Active Pixel Sensor (DMAPS) prototype

The simulation and verification framework developed by the RD53 collaboration is a powerful tool for global architecture optimization and design verification of next generation hybrid pixel readout chips. In this paper the framework is used for studying digital pixel chip architectures at behavioral level. This is carried out by simulating a dedicated, highly parameterized pixel chip description, which makes it possible to investigate different grouping strategies between pixels and different latency buffering and arbitration schemes. The pixel hit information used as simulation input can be either generated internally in the framework or imported from external Monte Carlo detector simulation data. The latter have been provided by both the CMS and ATLAS experiments, featuring HL-LHC operating conditions and the specifications related to the Phase 2 upgrade. Pixel regions and double columns were simulated using such Monte Carlo data as inputs: the performance of different latency buffering architectures was compared and the compliance of different link speeds with the expected column data rate was verified.

Test results of the Data Handling Processor for the DEPFET Pixel Vertex Detector

This work presents a depleted monolithic active pixel sensor (DMAPS) prototype manufactured in the LFoundry 150 nm CMOS process. The described device, named LF-Monopix, was designed as a proof of concept of a fully monolithic sensor capable of operating in the environment of outer layers of the ATLAS Inner Tracker upgrade for the High Luminosity Large Hadron Collider (HL-LHC). Implementing such a device in the detector module will result in a lower production cost and lower material budget compared to the presently used hybrid designs. In this paper the chip architecture will be described followed by the simulation and measurement results.

Simulation of digital pixel readout chip architectures with the RD53 SystemVerilog-UVM verification environment using Monte Carlo physics data

In order to extend its discovery potential, the Large Hadron Collider (LHC) will have a major upgrade (Phase II Upgrade) scheduled for 2022. The LHC after the upgrade, called High-Luminosity LHC (HL-LHC), will operate at a nominal leveled instantaneous luminosity of 5× 1034 cm−2 s−1, more than twice the expected Phase I . The new Inner Tracker needs to cope with this extremely high luminosity. Therefore it requires higher granularity, reduced material budget and increased radiation hardness of all components. A new pixel detector based on High Voltage CMOS (HVCMOS) technology targeting the upgraded ATLAS pixel detector is under study. The main advantages of the HVCMOS technology are its potential for low material budget, use of possible cheaper interconnection technologies, reduced pixel size and lower cost with respect to traditional hybrid pixel detector. Several first prototypes were produced and characterized within ATLAS upgrade R&D effort, to explore the performance and radiation hardness of this technology. In this paper, an overview of the HVCMOS sensor concepts is given. Laboratory tests and irradiation tests of two technologies, HVCMOS AMS and HVCMOS GF, are also given.

Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

In this paper, design details and simulation results of new pixel architectures designed in LFoundry 150 nm high voltage CMOS process in the framework of the ATLAS high luminosity inner detector upgrade are presented. These pixels can be connected to the FE-I4 readout chip via bump bonding or glue and some of them can also be tested without a readout chip. Negative high voltage is applied to the high resistivity (> 2 kΩ .cm) substrate in order to deplete the deep n-well charge collection diode, ensuring good charge collection and radiation tolerance. In these pixels, the front-end has been implemented inside the diode using both NMOS and PMOS transistors. The pixel pitch is 50 μm × 250 μm for all pixels. These pixels have been implemented in a demonstrator chip called LFCPIX.

HV/HR-CMOS sensors for the ATLAS upgrade-concepts and test chip results

We present the recent development of Depleted Monolithic Active Pixel Sensors (DMAPS), implemented with an LFoundry (LF) 150 nm CMOS process. MAPS detectors based on an epi-layer have been matured in recent years and have attractive features in terms of reducing material budget and handling cost compared to conventional hybrid pixel detectors. However, the obtained signal is relatively small (~1000 e−) due to the thin epi-layer, and charge collection time is relatively slow, e.g., in the order of 100 ns, because charges are mainly collected by diffusion. Modern commercial CMOS technology, however, offers advanced process options to overcome such difficulties and enable truly monolithic devices as an alternative to hybrid pixel sensors and charge coupled devices. Unlike in the case of the standard MAPS technologies with epi-layers, the LF process provides a high-resistivity substrate that enables large signal and fast charge collection by drift in a ~50 μm thick depleted layer. Since this process also enables the use of deep n- and p-wells to isolate the collection electrode from the thin active device layer, PMOS and NMOS transistors are available for the readout electronics in each pixel cell. In order to evaluate the sensor and transistor characteristics, several collection electrodes variants and readout architectures have been implemented. In this report, we focus on its design aspect of the LF-DMAPS prototype chip.

Pixel architectures in a HV-CMOS process for the ATLAS inner detector upgrade

Vertex detectors for High Energy Physics experiments require pixel detectors featuring high spatial resolution, very good signal to noise ratio and radiation hardness. A way to face new challenges of ATLAS/SLHC future hybrid pixel vertex detectors is to use the emerging 3-D Integrated Technologies. However, commercial offers of such technologies are only very few and the 3-D designers choice is then hardly constrained. Moreover, as radiation hardness and specially SEU tolerance of configuration registers is a crucial issue for SLHC vertex detectors and, as commercial data on this point are always missing, a reliable qualification program is to be developed for any candidate technology. We will present the design and test (including radiation tests with 70 kV, 60W X-Ray source and 24 GeV protons) of Chartered, 130nm Low Power 2-D chips realized for this qualification.