T. Ohzone

Blue electroluminescence from MOS capacitors with Si-implanted SiO/sub 2/

Abstract Electroluminescence (EL) spectra under direct-current (dc) operation are reported for Au/SiO 2 /p-Si MOS capacitors with 50 nm Si-implanted SiO 2 . The transparent Au gate not only improves measurable wavelength range but also suppresses interference effects among MOS layers. The clear and smooth EL spectra have been measured and the EL spectrum was analyzed by fitting five Gaussian distribution functions. A model of EL emission mechanism is proposed for the Si-implanted MOS EL device. Furthermore, photomicrograph of blue EL emission is given, and a possibility of visible light emitting microdisplay device is demonstrated.

A test structure for analysis of temperature distribution in stacked IC with sensing device array

A test structure for analysis of temperature distribution in stacked IC, which has a top tier chip attached on a bottom dummy chip with adhesive layer, is presented. The devices with four kinds of thickness of 50-410 um were fabricated. Dependences of the temperature on distance from the heater resistor were analyzed with on-chip sensor arrays, as well as fast transient phenomena. The thinner top tier structures showed the higher temperature and affected the temperature distributions. The test structure can provide an effective way for analysis of thermal properties in various LSIs.

A CMOS Temperature Sensor Circuit

A supply voltage (V DD ) independent temperature sensor circuit, which can be realized by the optimum combination of three current modes of n-MOSFETs including the subthreshold current using the feedback scheme from the temperature dependent voltage (V TD ) output to the gates of three n-MOSFETs, was proposed and fabricated by a standard 1.2μm n-well CMOS process. The circuit consists of only 17 MOSFETs without high resistors resulting in a small die area of 0.18 mm 2 . The temperature coefficient TC of the sensor circuit can be controlled by the channel length ratio L4/L 3 of two n-MOSFETs. The average temperature sensor voltage V TS and its typical TC are 1.77 V at V DD = 5.0 V (20°C) and 5.1 mV/°C for V DD = 5.0 ± 1.0 V in the temperature range of -20-100°C in case of L4/L3 = 9, respectively.

A test structure for reliability analysis of CMOS devices under DC and high frequency AC stress

A test structure for reliability analysis of MOSFETs in CMOS inverters under DC and high frequency AC stress has been presented. It has an input pulse generation block with a ring oscillator, monitor inverter blocks and Kelvin connected selector switches. Detailed I - V characteristics of MOSFETs in the monitor inverters were measured and the degradation by HCI and BTI in nMOS and pMOS devices were analyzed. The dominant degradation origins in nMOS and pMOS devices can be attributed to HCI and NBTI, respectively.

A Test Structure for Analysis of Asymmetry and Orientation Dependence of MOSFETs

A test structure to analyze asymmetry and orientation dependence of MOSFETs is presented. n-MOSFETs with 8 different channel orientation and three kinds of process conditions were measured and symmetry of IDsat and IBmax with respect to the interchange of source and drain was examined. Although both IDsat and IBmax have similar channel orientation dependence, only IBmax in interchanged S/D measurements shows asymmetrical characteristics, which can be applied to a sensitive method for device asymmetry detection.

Impact of Image and Exchange-Correlation Effects on Ballistic Electron Transport in Nanoscale Double-Gate Metal–Oxide–Semiconductor Transistors

The influence of image and many-body exchange-correlation effects on electron transport has been studied for nanoscale double-gate metal–oxide–semiconductor field-effect transistors (DG MOSFETs), using the non equilibrium Green function (NEGF) method. It has been found that the inclusion of image and exchange-correlation effects increases the calculated value of the drain current. This is because the potential energy is reduced except in some region around the surfaces, mainly due to the exchange-correlation effect. In this study, the wavefunction penetration into the gate oxide and gate electrode has also been taken into account. Compared to the case without considering this penetration, the electron occupancy of each valley type markedly changes though no substantial difference in the drain current is observed.

Reliability analysis of NAND gates with modified channel length in series n-MOSFETs

A channel length engineering technique for optimization of primitive cells in standard cell libraries is effective for a leakage reduction method without significant increase of delay time, maintaining the same cell size. Reliability of NAND gates with series n-MOSFETs, which have modified channel length, have been analyzed under voltage stress condition with a test structure of ring oscillator implemented in standard 90 nm CMOS process. Stress time tstrs dependence of degradation ratio of delay time td and operation current IOP follow a power law of tstrs. A channel length modification from 0.10 to 0.11 μm for the topmost n-MOSFET in series connected MOSFETs of NAND gates provides not only leakage current reduction but reliability improvement with less performance degradation under high voltage stress condition.

Orientation dependence and asymmetry of subthreshold characteristics in CMOSFETs

Orientation dependence and asymmetry of V<inf>T</inf> (threshold voltage), g<inf>m</inf> (transconductance), S (subthreshold slope), and I<inf>off</inf> (off-state current at V<inf>G</inf> =3D 0 V) in 0.18 μm n-MOSFETs were measured and analyzed. The test structure contains 8 different channel orientation angles of 0°/45°/90° and three kinds of process conditions. Although V<inf>T</inf>, g<inf>m</inf> and S scarcely show particular anisotropy except for the variation of MOSFET structure and/or impurity profile, the orientation dependence of GIDL characteristics is observed in the wafer with the higher extension dose.

A test structure for channel length engineering of NAND gates in standard cell library

A channel length engineering technique for optimization of primitive cells in standard cell libraries is proposed and a test structure to analyze the operation performance and leakage current of 3-input NAND is presented. Since the topmost transistor (Nl) in the three series connected n-MOSFETs of 3-input NAND has the largest VDS, subthreshold leakage current can be reduced by optimizing a channel length L of Nl. The leakage current of NANDs for input vector of (0, 1, 1) decreases by about 22 ~ 40 % with the change of L (Nl) from 0.1 to 0.11 mum. The channel length engineering of series connected MOSFETs provides a leakage reduction method for standard cells without significant increase of delay time, maintaining the same cell size.

A test structure to measure sheet resistances of highly-doped-drain and lightly-doped-drain in CMOSFET

A test structure to separately measure sheet resistances of highly-doped-drain (HDD) and lightly-doped-drain (LDD) in LDD-type CMOSFET with various gate spaces S having sub-100 nm sidewalls was proposed. The reciprocal of source/drain-resistance R/sup -1/ versus S characteristics show the unstable resistance variations in the narrower S regions, which suggest that the micro-loading or size effects seriously affect the characteristics.