Toshihiro Matsuda

Blue electroluminescence from MOS capacitors with Si-implanted SiO/sub 2/

Abstract Electroluminescence (EL) spectra under direct-current (dc) operation are reported for Au/SiO 2 /p-Si MOS capacitors with 50 nm Si-implanted SiO 2 . The transparent Au gate not only improves measurable wavelength range but also suppresses interference effects among MOS layers. The clear and smooth EL spectra have been measured and the EL spectrum was analyzed by fitting five Gaussian distribution functions. A model of EL emission mechanism is proposed for the Si-implanted MOS EL device. Furthermore, photomicrograph of blue EL emission is given, and a possibility of visible light emitting microdisplay device is demonstrated.

Electroluminescence of MOS capacitors with Si-implanted SiO2

Abstract Electroluminescence (EL) characteristics of n + -polysilicon MOS capacitors with 50 nm Si-implanted SiO 2 were measured. The EL intensity is almost proportional to the gate current, and the EL efficiency is about 50–70 times larger than that of a MOS capacitor without Si-implantation. Although the EL spectra of MOS capacitors have a broad peak around 650 nm regardless of the Si-implantation, only the EL intensity of Si-implanted MOS capacitors increases gradually below 500 nm. The latter may be caused by radiative electron capture into two kinds of SiO 2 trap levels, 2.0–2.5 and 3.0 eV below the conduction band of SiO 2 .

Erase/write cycle tests of n-MOSFETs with Si-implanted gate-SiO/sub 2/

To discuss the applicability of a MOSFET with Si-implanted gate-SiO/sub 2/ of 50 nm thickness to a non volatile random access memory (NVRAM) operating more than 3.3/spl times/10/sup 15/ erase/write (E/W) cycles, E/W-cycle tests were performed up to 10/sup 11/ cycles by measuring the hysteresis curve observed in a source follower MOSFET in which a sine-wave voltage of 100 kHz was supplied to the gate. Degradations in the threshold-voltage window of 15 V and gain factor were scarcely observed in a MOSFET with Si-implantation at 50 keV/1/spl times/10/sup 16/ cm/sup -2/ at a gate voltage of /spl plusmn/40 V. Those degradations observed in a MOSFET with 25 keV/3/spl times/10/sup 16/ cm/sup -2/ were improved by lowering the gate voltage from /spl plusmn/40 V to /spl plusmn/30 V in sacrificing the smaller threshold-voltage window from 20 to 8.5 V.

Study of the current–voltage characteristics in MOS capacitors with Si-implanted gate oxide

The specific gate current density (JG) versus voltage (VG) characteristics of MOS capacitors with 50 nm thick, implanted SiO2 (using various Si doses between 10 13 and 3 10 16 cm ˇ2 ) have been studied under inversion and accumulation conditions. From an analysis of dynamic resistance and current humps in the JG‐VG characteristics of the above devices, a qualitative model of the conduction mechanism has been proposed. Major current components in the model are the following: a direct tunnel current of electrons and holes related to traps generated by Siimplantation, a charging current of electrons and holes to traps distributed a little inside the gate oxide, a trapassisted current and a Fowler‐Nordheim tunnel current. The model can explain the JG‐VG curves and the change of the JG‐VG characteristics on the basis of the Si atomic distribution in the gate oxide. # 1999 Elsevier Science Ltd. All rights reserved.

A Temperature and Supply Voltage Independent CMOS Voltage Reference Circuit

A pure CMOS threshold-voltage reference (V TR ) circuit achieves temperature (T) coefficient of 5 μV/°C (T = -60 ∼ +100°C) and supply voltage (V DD ) sensitivity of 0.1 mV/V (V DD = 3 ∼ 5V). A combination of subthreshold current, linear current and saturation current in n-MOSFETs provides a small voltage and temperature dependence. Three different regions in I-V characteristics of MOSFETs generate a constant V TR based on threshold voltage at 0 K. A feedback scheme from the reference output to gates of n-MOSFETs extremely stabilizes the output. The circuit consists of only 17 MOSFETs and its simple scheme saves the die area, which is 0.18 mm 2 in the TEG (Test Element Group) chip fabricated by 1.2 μm n-well CMOS process.

Influence of image and exchange-correlation effects on electron transport in nanoscale DG MOSFETs

The impact of image and many-body exchange-correlation effects on electron transport has been investigated for nanoscale double-gate MOSFETs, using the nonequilibrium Green function method. The simulations have been performed for metal gate and polysilicon gate MOSFETs. When the gate material is metal, the inclusion of image and exchange-correlation effects increases the computed drain current, particularly at high gate voltages. In the case of polysilicon gate, the computed drain current remains almost unchanged at high gate voltages because both effects cancel out. However, at low gate voltages, the drain current is decreased by including these effects. In this study, the wavefunction penetration into the gate oxide and gate electrode has also been taken into account. Clear discrepancies between the drain currents calculated with and without considering the penetration effect can be found at low gate voltages. Further, the electron occupancy of each valley type is markedly changed by including this effect.

Electrical characteristics of 0/spl deg///spl plusmn/45/spl deg//90/spl deg/-orientation CMOSFET with source/drain fabricated by various ion-implantation methods

Electrical characteristics of 0/spl deg///spl plusmn/45/spl deg//90/spl deg/-orientation 0.5-/spl mu/m CMOSFETs with source/drain regions fabricated by three ion-implantation methods are discussed. For asymmetrical one-sided 7/spl deg/-implantation method, large-device-orientation dependent fluctuation and asymmetry were observed in (saturation drain current I/sub D/ and maximum substrate current I/sub B/ of both n- and p-MOSFETs/threshold voltage V/sub T/ of p-MOSFETs) and (I/sub D/ of n-MOSFETs/I/sub B/ of both n- and p-MOSFETs), respectively. Almost comparable characteristics were obtained for n-MOSFETs fabricated by symmetrical 0/spl deg/-implantation and 7/spl deg//spl times/4-implantation methods. However, I/sub D/ difference in p-MOSFETs between 0/spl deg//90/spl deg/- and /spl plusmn/45/spl deg/-orientation devices, which may be affected by intraplanar anisotropy of hole drift velocity, was observed independently of the ion-implantation method.

A V/sub DD/ and temperature independent CMOS voltage reference circuit

A pure CMOS threshold voltage reference (V_TR)circuit achieves temperature(T) coefficient of 5 μV/°C (T=60~+100 °C) and supply voltage(V_DD) sensitivity of O.1 mV/V (V_DD=3-5 V). The combination of subthreshold current characteristics and different operating modes in n-MOSFETs provides a small voltage and temperature dependence. A feedback scheme from the reference output to gates of n-MOSFETs not only stabilizes the output but also saves the die area.

Influence of asymmetric/symmetric source/drain region on asymmetry and mismatch of CMOSFET's and circuit performance

Experimental results on asymmetry and mismatch (A&M) characteristics are discussed for 0.5-/spl mu/m surface-channel n-MOSFETs and buried-channel p-MOSFETs fabricated with four ion-implantation methods and designed with a conventional and a side-by-side layout. The side-by-side layout is useful to improve A&M caused by source/drain asymmetry in MOSFETs with a one-sided 7/spl deg/-implantation method. The symmetric 7/spl deg//spl times/4-implantation method gives good A&M characteristics of n- and p-MOSFETs with the both layouts. According to the circuit performance of ring oscillators, the ion-implantation method is correlated to supply-current/oscillation-frequency/delay-power product and substrate current. The symmetric 7/spl deg//spl times/4-implantation method is the most preferable in terms of A&M and punchthrough immunity of CMOSFET as well as circuit performance.

Time dependent dielectric breakdown characteristics of MOS capacitors with Si-implanted SiO2

Abstract The current-voltage and time dependent dielectric breakdown characterics of MOS capacitors with various Si-implanted SiO 2 layers of 50 nm thickness were measured at inversion and accumulation condition. In comparison with unimplanted SiO 2 , some implanted SiO 2 samples have a higher breakdown voltage and a maximum allowable constant voltage or current stress for a 10-year life-time. The latter suggests the possibility of SiO 2 electrical characteristics engineering by Si-implantation.