T.P. Van Doren

Power bus decoupling on multilayer printed circuit boards

Guidelines for the selection and placement of decoupling capacitors that work well for one-sided or two-sided printed circuit boards are not appropriate for multilayer boards with power and ground planes. Boards without internal planes take advantage of the power bus inductance to help decouple components at the higher frequencies. An effective decoupling strategy for multilayer boards must account for the low inductance and relatively high capacitance of the power bus. >

Quantifying SMT decoupling capacitor placement in dc power-bus design for multilayer PCBs

Noise on a dc power-bus that results from device switching, as well as other potential mechanisms, is a primary source of many signal integrity (SI) and electromagnetic interference (EMI) problems. Surface mount technology (SMT) decoupling capacitors are commonly used to mitigate this power-bus noise. A critical design issue associated with this common practice in high-speed digital designs is placement of the capacitors with respect to the integrated circuits (ICs). Local decoupling, namely, placing SMT capacitors in proximity to ICs, is investigated in this study. Multilayer PCB designs that employ entire layers or area fills for power and ground in a parallel plate structure are considered. The results demonstrate that local decoupling can provide high-frequency benefits for certain PCB geometries through mutual inductive coupling between closely spaced vias. The associated magnetic flux linkage is between the power and ground layers. Numerical modeling using an integral equation formulation with circuit extraction is used to quantify the local decoupling phenomenon. Local decoupling can effectively reduce high-frequency power-bus noise, though placing capacitors adjacent to ICs may limit routing flexibility, and tradeoffs need to be made based on design requirements. Design curves are generated as a function of power-bus layer thickness and SMT capacitor/IC spacing using the modeling approach to quantify the power-bus noise reduction for decoupling capacitors located adjacent to devices. Measurement data is provided to corroborate the modeling approach.

Numerical modeling of electrostatic discharge generators

The discharge current and the transient fields of an electrostatic discharge (ESD) generator in the contact mode are numerically simulated using the finite-difference time-domain method. At first the static field is established. Then the conductivity of the relay contact is changed, which initiates the discharge process. The simulated data are used to study the effect of design choices on the current and fields. They are compared to measured field and current data using a multidecade broadband field and current sensors. The model allows accurate prediction of the fields and currents of ESD generators, thus it can be used to evaluate different design choices.

Power-bus decoupling with embedded capacitance in printed circuit board design

This paper experimentally investigates the effectiveness of embedded capacitance for reducing power-bus noise in high-speed printed circuit board designs. Boards with embedded capacitance employ closely spaced power-return plane pairs separated by a thin layer of dielectric material. In this paper, test boards with four embedded capacitance materials are evaluated. Power-bus input impedance measurements and power-bus noise measurements are presented for boards with various dimensions and layer stack ups. Unlike discrete decoupling capacitors, whose effective frequency range is generally limited to a few hundred megahertz due to interconnect inductance, embedded capacitance was found to efficiently reduce power-bus noise over the entire frequency range evaluated (up to 5 GHz).

Numerical and experimental corroboration of an FDTD thin-slot model for slots near corners of shielding enclosures

Simple design maxims to restrict slot dimensions in enclosure designs below a half-wave length are not always adequate for minimizing electromagnetic interference (EMI). Complex interactions between cavity modes, sources, and slots can result in appreciable radiation through nonresonant length slots. The finite-difference time domain (FDTD) method can be employed to pursue these issues with adequate modeling of thin slots. Subcellular FDTD algorithms for modeling thin slots in conductors have previously been developed. One algorithm based on a quasistatic approximation has been shown to agree well with experimental results for thin slots in planes. This FDTD thin-slot algorithm is compared herein with two-dimensional (2-D) moment method results for thin slots near corners and plane wave excitation. FDTD simulations are also compared with measurements for slots near an edge of a cavity with an internal source.

Power bus noise reduction using power islands in printed circuit board designs

Power islands are often used to isolate devices that put noise on a power bus from devices that may be susceptible to power bus noise. At high frequencies however, the effectiveness of these islands depends on the implementation. This paper experimentally investigates the effectiveness of different power island structures at frequencies up to 3 GHz.

RF isolation using power islands in DC power bus design

Power island structures are often employed for minimizing the propagation of high-frequency noise on DC power buses. The rationale is based on introducing a series impedance in the power plane to provide isolation of a noise source from the rest of the PCB design. The power island concept is investigated herein experimentally, to determine its noise mitigation attributes and limitations. A modeling approach that is suitable for arbitrary PCB island geometries including lumped SMT decoupling capacitors is also presented. The modeling and measurements indicate that island structures can achieve some degree of isolation under certain conditions.

Power bus isolation using power islands in printed circuit boards

Power islands are often employed in printed circuit board (PCB) designs to alleviate the problem of power bus noise coupling between circuits. Good isolation can be obtained over a wide frequency band due to the large series impedance provided by the gap between the power islands. However, power bus resonances may degrade the isolation at high frequencies. The amount of isolation also depends on the type of connection between power islands and the components on the board. This paper experimentally investigates the effectiveness of several power island structures up to 3.0 GHz.

Modeling multilayered PCB power-bus designs using an MPIE based circuit extraction technique

A circuit extraction tool (CEMPIE) has been developed based on the mixed-potential integral equation (MPIE) using a quasi-static approximation. A power-bus in a multi-layered PCB consisting of a pair of dedicated ground and power planes is studied using this tool. The distributed behavior of a power-bus is represented by a collection of passive circuit elements, which is valid up to several gigahertz. The decoupling performance of a power-bus due to its layer spacing and the dielectric constant is evaluated for simple test geometries. The impact of the relative distance between the noise source and the potential receiver is also studied. Novel structures such as a power island were studied in both thin and thick boards, and the decoupling performance due to the locations and values of the decoupling capacitors were also investigated.

Traces in proximity to gaps in return planes

Coupling between circuitry on printed circuit boards can be mitigated by a variety of well-known techniques. One such technique is to isolate circuitry in different areas of the printed circuit board by strategically placing a gap in the signal return plane. However, this technique is only effective at reducing common-impedance coupling, which is generally not a significant coupling mechanism at frequencies above 1 MHz. This paper investigates the effect of a gap located between and parallel to adjacent microstrip traces. The effect of the gap on the mutual inductance and mutual capacitance is evaluated. Laboratory measurements and numerical simulations show that gaps in the return plane are ineffective at reducing inductive and capacitive crosstalk in most configurations, and in some cases they increase the mutual coupling between printed circuit board traces.