Todd H. Hubing

Power bus decoupling on multilayer printed circuit boards

Guidelines for the selection and placement of decoupling capacitors that work well for one-sided or two-sided printed circuit boards are not appropriate for multilayer boards with power and ground planes. Boards without internal planes take advantage of the power bus inductance to help decouple components at the higher frequencies. An effective decoupling strategy for multilayer boards must account for the low inductance and relatively high capacitance of the power bus. >

The Electromagnetic Compatibility of Integrated Circuits—Past, Present, and Future

Throughout the decades of continuous advances in semiconductor technology, from the discrete devices of the late 1950s to todays billon-transistor system-on-chip, there have always been concerns about the ability of components to operate safely in an increasingly disruptive electromagnetic environment. This paper provides a nonexhaustive review of the research work conducted in the field of electromagnetic compatibility (EMC) at the IC level over the past 40 years. It also brings together a collection of information and trends in IC technology, in order to build a tentative roadmap for the EMC of ICs until the year 2020, with a focus on measurement methods and modeling approaches.

Quantifying SMT decoupling capacitor placement in dc power-bus design for multilayer PCBs

Noise on a dc power-bus that results from device switching, as well as other potential mechanisms, is a primary source of many signal integrity (SI) and electromagnetic interference (EMI) problems. Surface mount technology (SMT) decoupling capacitors are commonly used to mitigate this power-bus noise. A critical design issue associated with this common practice in high-speed digital designs is placement of the capacitors with respect to the integrated circuits (ICs). Local decoupling, namely, placing SMT capacitors in proximity to ICs, is investigated in this study. Multilayer PCB designs that employ entire layers or area fills for power and ground in a parallel plate structure are considered. The results demonstrate that local decoupling can provide high-frequency benefits for certain PCB geometries through mutual inductive coupling between closely spaced vias. The associated magnetic flux linkage is between the power and ground layers. Numerical modeling using an integral equation formulation with circuit extraction is used to quantify the local decoupling phenomenon. Local decoupling can effectively reduce high-frequency power-bus noise, though placing capacitors adjacent to ICs may limit routing flexibility, and tradeoffs need to be made based on design requirements. Design curves are generated as a function of power-bus layer thickness and SMT capacitor/IC spacing using the modeling approach to quantify the power-bus noise reduction for decoupling capacitors located adjacent to devices. Measurement data is provided to corroborate the modeling approach.

Power-bus decoupling with embedded capacitance in printed circuit board design

This paper experimentally investigates the effectiveness of embedded capacitance for reducing power-bus noise in high-speed printed circuit board designs. Boards with embedded capacitance employ closely spaced power-return plane pairs separated by a thin layer of dielectric material. In this paper, test boards with four embedded capacitance materials are evaluated. Power-bus input impedance measurements and power-bus noise measurements are presented for boards with various dimensions and layer stack ups. Unlike discrete decoupling capacitors, whose effective frequency range is generally limited to a few hundred megahertz due to interconnect inductance, embedded capacitance was found to efficiently reduce power-bus noise over the entire frequency range evaluated (up to 5 GHz).

Model for estimating radiated emissions from a printed circuit board with attached cables due to Voltage-driven sources

Common-mode currents induced on cables attached to printed circuit boards (PCBs) can be a significant source of unintentional radiated emissions. This paper develops a model for estimating the amount of common-mode cable current that can be induced by the signal voltage on microstrip trace structures or heatsinks on a PCB. The model employs static electric field solvers or closed-form expressions to estimate the effective self-capacitances of the board, trace, and/or heatsink. These capacitances are then used to determine the amplitude of an equivalent common-mode voltage source that drives the attached cables. The model shows that these voltage-driven common-mode cable currents are relatively independent of the cable parameters and the trace or heatsink location when the PCB is small relative to the cable length and to a wavelength.

The development of a closed-form expression for the input impedance of power-return plane structures

In multilayer printed circuit boards, the noise on the power bus is influenced by the impedance between the power and ground planes. Power-bus noise estimates require an accurate estimate of the power-bus input impedance. This paper develops a closed-form estimate of the input impedance for circular power-return plane structures. When the structure is lossy (e.g., boards employing embedded capacitance or densely populated boards), the energy reflected from the board edge does not significantly affect the input impedance. In general, the expressions developed here for circular structures can be used to estimate the impedance of lossy power-return plane structures of any shape.

Numerical and experimental corroboration of an FDTD thin-slot model for slots near corners of shielding enclosures

Simple design maxims to restrict slot dimensions in enclosure designs below a half-wave length are not always adequate for minimizing electromagnetic interference (EMI). Complex interactions between cavity modes, sources, and slots can result in appreciable radiation through nonresonant length slots. The finite-difference time domain (FDTD) method can be employed to pursue these issues with adequate modeling of thin slots. Subcellular FDTD algorithms for modeling thin slots in conductors have previously been developed. One algorithm based on a quasistatic approximation has been shown to agree well with experimental results for thin slots in planes. This FDTD thin-slot algorithm is compared herein with two-dimensional (2-D) moment method results for thin slots near corners and plane wave excitation. FDTD simulations are also compared with measurements for slots near an edge of a cavity with an internal source.

Power bus noise reduction using power islands in printed circuit board designs

Power islands are often used to isolate devices that put noise on a power bus from devices that may be susceptible to power bus noise. At high frequencies however, the effectiveness of these islands depends on the implementation. This paper experimentally investigates the effectiveness of different power island structures at frequencies up to 3 GHz.

RF isolation using power islands in DC power bus design

Power island structures are often employed for minimizing the propagation of high-frequency noise on DC power buses. The rationale is based on introducing a series impedance in the power plane to provide isolation of a noise source from the rest of the PCB design. The power island concept is investigated herein experimentally, to determine its noise mitigation attributes and limitations. A modeling approach that is suitable for arbitrary PCB island geometries including lumped SMT decoupling capacitors is also presented. The modeling and measurements indicate that island structures can achieve some degree of isolation under certain conditions.

Imbalance Difference Model for Common-Mode Radiation From Printed Circuit Boards

The differential-mode signals in printed circuit board (PCB) traces are unlikely to produce significant amounts of radiated emissions directly; however these signals may induce common-mode currents on attached cables, enclosures, or heat sinks that result in radiated electromagnetic (EM) interference. Full-wave EM modeling can be performed in order to determine the level of radiated emissions produced by a PCB, but this modeling is computationally demanding and does not provide the physical insight necessary to explain how differential signals induce common-mode currents on distant objects. This paper describes a model for determining the common-mode currents on cables attached to a PCB that is based on the concept of imbalance difference . The imbalance difference model is derived from research that shows that changes in geometrical imbalance cause differential- to common-mode conversion. This paper applies an imbalance difference model to PCB structures and compares the resulting equivalent source configurations to those obtained with traditional voltage- and current-driven models, as well as full-structure simulations.