T. Salo

80-MHz bandpass /spl Delta//spl Sigma/ modulators for multimode digital IF receivers

Three fully differential bandpass (BP) /spl Delta//spl Sigma/ modulators are presented. Two double-delay resonators are implemented using only one operational amplifier. The prototype circuits operate at a sampling frequency of 80 MHz. The BP /spl Delta//spl Sigma/ modulators can be used in an intermediate-frequency (IF) receiver to combine frequency downconversion with analog-to-digital conversion by directly sampling an input signal from an IF of 60 MHz to a digital IF of 20 MHz. The measured peak signal-to-noise-plus-distortion ratios are 78 dB for 270 kHz (GSM), 75 dB for 1.25 MHz (IS-95), 69 dB for 1.762 MHz (DECT), and 48 dB for 3.84 MHz (WCDMA/CDMA2000) bandwidths. The circuits are implemented with a 0.35-/spl mu/m CMOS technology and consume 24-38 mW from a 3.0-V supply, depending on the architecture.

A 80-MHz bandpass /spl Delta//spl Sigma/ modulator for a 100-MHz IF receiver

A fully differential fourth-order bandpass /spl Delta//spl Sigma/ modulator is presented. The circuit is targeted for a 100-MHz GSM/WCDMA-multimode IF-receiver and operates at a sampling frequency of 80 MHz. It combines frequency downconversion with analog-to-digital conversion by directly sampling an input signal from an intermediate frequency of 100 MHz to a digital intermediate frequency of 20 MHz. The modulator is based on a double-delay single-op amp switched-capacitor (SC) resonator structure which is well suited for low supply voltages. Furthermore, the center frequency of the topology is insensitive to different component nonidealities. The measured peak signal-to-noise ratio is 80 and 42 dB for 270 kHz (GSM) and 3.84-MHz (WCDMA) bandwidths, respectively. The circuit is implemented with a 0.35-/spl mu/m CMOS technology and consumes 56 mW from a 3.0-V supply.

Fully integrated charge sensitive amplifier for readout of micromechanical capacitive sensors

This paper presents a charge sensitive amplifier (CSA) for readout of micromechanical capacitive sensors. The transfer function and noise performance together with noise optimisation are studied from a theoretical point of view. The feedback resistors of the CSA are implemented as long-channel MOS transistors to set the -3 dB corner frequency well below 1 kHz. The common-mode feedback is designed to keep the input common-mode level constant to achieve an accurate gain from the change in capacitance to output signal. A CSA was designed and implemented for the readout of a bulk micromachined gyroscope with a resonance frequency of 8-10 kHz and signal bandwidth of 100 Hz. A measured resolution of 2.47-3.00 aF (rms) in capacitance change integrated over the signal band is achieved. The CSA tolerates leakage currents of over 5 nA at its input.

Integrated Readout and Control Electronics for a Microelectromechanical Angular Velocity Sensor

An ASIC is implemented for readout and control of a bulk micromachined capacitive gyroscope. Both the system architecture and details on the circuitry of different subsystems are presented. Together with digital signal processing on an FPGA chip, a complete working prototype of a microelectromechanical gyroscope is realized and measured. This plusmn100 deg/s gyroscope achieves 0.053 deg/s/yradic(Hz) spot noise and 49.9 dB signal-to-noise ratio over the 36 Hz bandwidth, with plusmn4 % offset stability over the temperature range from -40 to +85 degC. The work shows that a gyroscope can be realized with the chosen architecture, and that good performance can be achieved

Readout and Control Electronics for a Microelectromechanical Gyroscope

In this paper, the system-level implementation of readout and control electronics for a microelectromechanical angular velocity sensor will be presented. The sensor element for which the electronics is designed is a bulk micromachined silicon device with electrostatic detection and excitation. The electronics is divided into two parts, analog and digital. Analog electronics is implemented with a 0.7 mum CMOS process that offers high voltage devices and precision analog components. Digital signal processing is implemented with a field-programmable gate array chip. One of the most important system-level nonidealities, the zero-rate output, is analysed, paying attention to its effects on the electronics design. The implemented plusmn100deg/s angular velocity sensor achieves 0.053deg/s/radicHz measured spot noise and 49.9 dB signal-to-noise ratio over the 36 Hz bandwidth, with plusmn4% zero-rate output stability over the temperature range from -40 to +85 degC

A double-sampling SC-resonator for low voltage bandpass /spl Delta//spl Sigma/-modulators

In this paper, a novel double-sampling switched-capacitor (SC)-resonator with high performance is proposed. The quality factors of the resonators, high notch Q-value and the accurate notch frequency, are analyzed at the transfer function level. Furthermore, their effect on the quantization noise shaping in the implementation of the BP /spl Delta//spl Sigma/-modulator is explained. Discrete-time resonator topologies are discussed and the double delay resonator structure is shown to have potential to implement high performance resonators. A double-sampling switched-capacitor resonator is presented with comparisons to reported structures. The nonidealities are analyzed in the light of the preceding theoretical scrutiny. The structure is found to be very insensitive to imperfections of the analog circuits and it has a low capacitive load leading to a low power consumption. Finally, a BP /spl Delta//spl Sigma/-modulator using the proposed resonator is presented along with behavioral level simulation results.

Readout Electronics with Bandpass Delta-Sigma A/D Converter for a Bulk Micromachined Capacitive Gyroscope

This paper presents a fully integrated readout electronics designed for a bulk micromochined capacitive gynoscope. The readout chain is composed of a charge sensitive amplifer, analog signal processing and a δσ-type A/D converter. The analog signal processing consists of a high-pass filter, a variable-gain amplifier, another high-pass filter and a low-pass filter. The system achieves a measured capacitance sensitivity of 4.00 aF (rms) in a 100 Hz band centered at 8.462kHz, consuming 2.9 mA. The signal frequency can vary between 8-10 kHz, depending on the gyroscope element. A full microelectromechanical angular velocity sensor system has been built using the readout electronics described together with external electronics, and its operation has been verified.

A low-voltage single-Opamp 4th-order band-pass /spl Delta//spl Sigma/-modulator

A band-pass /spl Delta//spl Sigma/-modulator can be used to directly digitize the IF signal in a radio receiver. As the resolution and the channel bandwidth of a band-pass /spl Delta//spl Sigma/-modulator can easily be traded afterwards, it is the key circuit block in implementing receivers for future multi-mode mobile phones. However, the reported implementations have been based on resonator structures which are poorly suited to a low supply voltage which has led to high power consumptions. A switched-capacitor double-delay resonator structure which imposes no limitation on the Opamp output scaling is proposed. The structure allows the optimization of Opamp output swings with no power penalty and is thus ideally suited for low supply voltage. A single Opamp bandpass /spl Delta//spl Sigma/-modulator which shares the Opamp between two double-delay resonators is presented along with behavioral level simulation results. According to the simulations the presented BP /spl Delta//spl Sigma/-modulator achieves 14 b-resolution for the GSM-channel bandwidth (BW=270 kHz) and 6 b-resolution for the WCDMA-channel bandwidth (BW=3.84 MHz).

A 2.7 V CMOS dual-mode baseband filter for GSM and WCDMA

A 5th order analog CMOS continuous-time baseband filter for a dual-mode cellular phone was designed with maximum component sharing in the two modes. The filter was designed to meet the bandwidth requirements of both GSM and WCDMA standards. The area was minimized by using common capacitance matrices and operational amplifiers in the two modes. Operational amplifiers with a programmable GBW were used in order to minimize the power consumption in GSM-mode. The real pole of both fifth order transfer functions was realized as a passive integrated structure and a ladder filter was used to realize the two remaining complex pole pairs. This helped to reduce the power consumption further while resulting in a very low input referred noise. A 7-step gain tuning was implemented with tunable transconductance stage between the passive RC-loop and the active ladder structure. The measured frequency responses are in good agreement with simulations. The measured integrated input referred noise was 6.9 /spl mu/V and 13.6 /spl mu/V in the GSM- and WCDMA-modes, respectively. The IIP3 was +25 dBV in the WCDMA-mode and the circuit consumed 13.0 mW and 21.8 mW in the GSM- and WCDMA-modes, respectively.

A dual-mode 80 MHz bandpass /spl Delta//spl Sigma/ modulator for a GSM/WCDMA IF-receiver

The authors present a band-pass modulator operating at 80 MHz which combines frequency down-conversion with A/D conversion. The two SC resonators are implemented using a single opamp. A single-bit quantizer and feedback is used for GSM, but 4 b quantizer is used for WCDMA. Measured peak SNRs are 80 dB for 270 kHz B/W (GSM), and 48 dB for 3.84 MHz B/W (WCDMA).