Saska Lindfors

A 60-GHz CMOS receiver with an on-chip ADC

A broadband 60-GHz receiver implemented in a 65-nm baseline CMOS technology is presented. A millimeter-wave front-end, including a single-ended low noise amplifier and a balanced resistive mixer, an IF-stage and an analog baseband circuit with an analog-to-digital converter are integrated on a single chip. The receiver achieves a measured 7.0-dB noise figure at 60 GHz and the voltage gain can be controlled between 45 to 79 dB. The measured 1-dB input compression point is −38.5 dBm.

A digital frequency synthesizer for cognitive radio spectrum sensing applications

This paper presents a wideband digital frequency synthesizer architecture targeted for spectrum sensing applications. The proposed frequency synthesizer architecture is based on digital period synthesis (DPS), which inherently can achieve a wide operational bandwidth, extremely high-frequency resolution, and an instantaneous settling time with low power and area consumption. The performance of DPS and its fundamental limitations are analyzed in this paper. The frequency synthesizer was implemented in a 65-nm CMOS process and it occupies an active area of 0.12 mm2 . The frequency range of the synthesizer is from 0.1 to 4.267 GHz with a frequency resolution of 0.025-5.38 Hz. In this frequency range, the power consumption is between 3.6-8.4 mW.

Continuous-Time Low-Pass Filters for Integrated Wideband Radio Receivers

Aalto University, P.O. Box 11000, FI-00076 Aalto www.aalto.fi Author Ville Saari Name of the doctoral dissertation Continuous-time low-pass filters for integrated wideband radio receivers Publisher School of Electrical Engineering Unit Department of Microand Nanosciences Series Aalto University publication series DOCTORAL DISSERTATIONS 23/2011 Field of research Electronic Circuit Design Manuscript submitted 21.06.2010 Manuscript revised 17.12.2010 Date of the defence 29.04.2011 Language English Monograph Article dissertation (summary + original articles) Abstract This thesis concentrates on the design and implementation of analog baseband continuoustime low-pass filters for integrated wideband radio receivers. A total of five experimental analog baseband low-pass filter circuits were designed and implemented as a part of five single-chip radio receivers in this work. After the motivation for the research work presented in this thesis has been introduced, an overview of analog baseband filters in radio receivers is given first. In addition, a review of the three receiver architectures and the three wireless applications that are adopted in the experimental work of this thesis is presented. The relationship between the integrator nonidealities and integrator Q-factor, as well as the effect of the integrator Q-factor on the filter frequency response, are thoroughly studied on the basis of a literature review. The theoretical study that is provided is essential for the gm-C filter synthesis with non-ideal lossy integrators that is presented after the introduction of different techniques to realize integrator-based continuous-time low-pass filters. The filter design approach proposed for gm-C filters is original work and one of the main points in this thesis, in addition to the experimental IC implementations. Two evolution versions of fourth-order 10-MHz opamp-RC low-pass filters designed and implemented for two multicarrier WCDMA base-station receivers in a 0.25-um SiGe BiCMOS technology are presented, along with the experimental results of both the low-pass filters and the corresponding radio receivers. The circuit techniques that were used in the three gm-C filter implementations of this work are described and a common-mode induced even-order distortion in a pseudo-differential filter is analyzed. Two evolution versions of fifth-order 240-MHz gm-C low-pass filters that were designed and implemented for two single-chip WiMedia UWB direct-conversion receivers in a standard 0.13-um and 65-nm CMOS technology, respectively, are presented, along with the experimental results of both the lowpass filters and the second receiver version. The second UWB filter design was also embedded with an ADC into the baseband of a 60-GHz 65-nm CMOS radio receiver. In addition, a thirdorder 1-GHz gm-C low-pass filter was designed, rather as a test structure, for the same receiver. The experimental results of the receiver and the third gm-C filter implementation are presented.This thesis concentrates on the design and implementation of analog baseband continuoustime low-pass filters for integrated wideband radio receivers. A total of five experimental analog baseband low-pass filter circuits were designed and implemented as a part of five single-chip radio receivers in this work. After the motivation for the research work presented in this thesis has been introduced, an overview of analog baseband filters in radio receivers is given first. In addition, a review of the three receiver architectures and the three wireless applications that are adopted in the experimental work of this thesis is presented. The relationship between the integrator nonidealities and integrator Q-factor, as well as the effect of the integrator Q-factor on the filter frequency response, are thoroughly studied on the basis of a literature review. The theoretical study that is provided is essential for the gm-C filter synthesis with non-ideal lossy integrators that is presented after the introduction of different techniques to realize integrator-based continuous-time low-pass filters. The filter design approach proposed for gm-C filters is original work and one of the main points in this thesis, in addition to the experimental IC implementations. Two evolution versions of fourth-order 10-MHz opamp-RC low-pass filters designed and implemented for two multicarrier WCDMA base-station receivers in a 0.25-um SiGe BiCMOS technology are presented, along with the experimental results of both the low-pass filters and the corresponding radio receivers. The circuit techniques that were used in the three gm-C filter implementations of this work are described and a common-mode induced even-order distortion in a pseudo-differential filter is analyzed. Two evolution versions of fifth-order 240-MHz gm-C low-pass filters that were designed and implemented for two single-chip WiMedia UWB direct-conversion receivers in a standard 0.13-um and 65-nm CMOS technology, respectively, are presented, along with the experimental results of both the lowpass filters and the second receiver version. The second UWB filter design was also embedded with an ADC into the baseband of a 60-GHz 65-nm CMOS radio receiver. In addition, a thirdorder 1-GHz gm-C low-pass filter was designed, rather as a test structure, for the same receiver. The experimental results of the receiver and the third gm-C filter implementation are presented.

Prototype and Synthesis of Active Filters

At the very beginning of the filter design, an appropriate filter transfer function and the order of the filter have to be selected. In radio receivers, the bandwidth and, particularly, the selectivity requirement for channel-select and anti-aliasing filtering are determined by the wireless application being targeted, the specified or expected interferers scenario, and the performance of the ADC, as discussed in Chap. 2. The bandwidth and selectivity requirements of the analog baseband filter further depend on the receiver architecture adopted and the preceding filter stages. The filter transfer function and the order of the filter are then chosen according to the given selectivity requirement. In addition, for example, the passband flatness and phase response characteristics that are required have to be taken into account. In active filter implementations, the minimization of filter stages (i.e. the order of the filter) is typically beneficial in terms of noise, power consumption, and complexity. Therefore, it is important also to consider the feasibility of the active filter realization, as well as the performance requirements set for the filter block, before finally deciding on the filter prototype.

Active polyphase filter analysis

This paper describes the analysis and design of active polyphase filters. Analysis for 1- and 2-stage filters are carried out in this paper with simplified transconductance models. Gain and stability, which differentiate the active and passive filters, are analyzed and presented as a function of the key design parameters of the transconductance element and of the filter. Additionally an analytical expression for the 2-stage stability is presented. A design example is given to demonstrate the use of the analysis results. The work presented provides tools for designing active polyphase filters in terms of gain, stability and image rejection ratio.

Opamp-RC Filters for Multicarrier WCDMA Base-Station Receivers

This chapter describes the circuit design of two evolution versions of continuous-time opamp-RC low-pass filters that were implemented in this work as a part of two single-chip multicarrier UTRA FDD WCDMA base-station receivers. Hereafter UTRA FDD WCDMA is called simply WCDMA. The two opamp-RC low-pass filters that were designed, implemented, and measured and are included in this chapter are original work in this book, previously published in [1] and [2]. The corresponding versions of the multicarrier receiver IC implementations were previously reported with experimental results in [3] and [4]. To the best of the authors’ knowledge, the former is the first published single-chip multicarrier WCDMA receiver implementation. Since the main interest in this book is in the design and implementation of continuous-time low-pass filters for integrated radio receivers, rather than concentrating on stand-alone filter circuits, both multicarrier receiver implementations are also briefly presented in this chapter. Moreover, since the operation of the opamp-RC low-pass filters that were designed being embedded in a single-chip radio receiver affects the overall performance of the receiver, the experimental results of both the low-pass filters and the multicarrier receivers are shown at the end of this chapter. This chapter is mainly based on the contents of the four publications cited above.

Gm-C Filters for CMOS Direct-Conversion Receivers

The purpose of this chapter is to give a detailed description of circuit techniques that were used in this work in the three gm-C filter implementations, of which the experimental results are presented in Chap. 7. Consequently, the focus is on circuit techniques that are suitable for use when designing and implementing low-voltage wideband analog low-pass filters with programmable voltage gain in standard ultra-deep-submicron (<0.2-μm) or nanoscale (sub-100-nm) CMOS technologies. The low supply voltage (≈1.2 V) of the modern CMOS technologies limits the voltage swing and, thus, the dynamic range in analog integrated circuits. The voltage headroom can be increased by reducing the number of stacked transistors. Therefore, in this work, the functionality of the main signal processing circuits was improved by employing parallel-connected control circuits instead of using, for example, cascode transistors or other conventional circuit solutions previously utilized with higher supply voltages. Some of the circuit techniques that are presented in this chapter have been developed in this work. Parts of them are improved or modified versions of circuits previously proposed by others that were tailored in this work to fulfill the needs determined by the low-voltage wideband receiver applications adopted in this work. This chapter is mainly based on the contents of publications [1] and [2].

Integrated Continuous-Time Low-Pass Filters

Integrated continuous-time filters are most often constructed from inverting and non-inverting lossy and lossless integrators [1–5]. In addition, summers or related circuits are typically needed to add two or more signals together, thereby completing the structure of the filter. These integrator-based active filters are suitable for integration at the baseband since, contrary to their passive LC ladder counterparts, they do not employ passive inductors. As explained in more detail in, for example, [3, 6, 7], at (low) baseband frequencies, integrated passive inductors easily occupy an impractically large die area. Moreover, their Q-factor tends to be low, preventing the implementation of highly selective passive filters [8]. In wideband applications, in which the low-pass filters to be designed are required to have, let us say, a bandwidth of over 100 MHz, the integration of passive LC ladder filters may be considered [9]. However, this book addresses the design and implementation of integrator-based active continuous-time low-pass filters.

Overview of Analog Baseband Filters in Radio Receivers

In this work, the analog baseband low-pass filter is defined as the receiver block between the RF front-end and the analog-to-digital converter (ADC). In a superheterodyne receiver, however, it is placed between the IF stage and the ADC, to be exact. The analog baseband filter is responsible for performing channel-select filtering, either partially with the digital back-end or completely in the analog domain. In addition, the preceding receiver stages may also include passive filters, potentially alleviating the selectivity, and, especially, the stopband linearity requirements of the analog baseband filter. The partitioning of the filtering in a radio receiver depends on the receiver architecture selected, the gain and the linearity of the receiver building blocks employed, and the wireless application that is targeted, including the interferer scenario. The analog baseband filter can be a continuous-time or a discrete-time filter. Continuous-time filters have a speed advantage when compared to their discrete-time counterparts, since no sampling is required [1–3]. Therefore, it is often the case that continuous-time filters are more suitable for wideband applications. Moreover, the following ADC requires anti-aliasing filtering, which can be performed only by continuous-time filters. To accomplish simultaneous channel-select and anti-aliasing filtering and hence to reduce the number of power-consuming and noisy filter stages in a receiver, the employment of continuous-time low-pass filters is a practical choice. This work concentrates on the design and implementation of continuous-time filters and, thus, discrete-time filters are excluded from this book.

Experimental CMOS Gm-C Filter Circuits

In this chapter, a total of three continuous-time gm-C low-pass filter implementations are presented, together with their measured performance. They include two evolution versions of fifth-order 240-MHz gm-C filters that were designed and implemented in this work as a part of two single-chip WiMedia UWB direct-conversion receivers in a standard 0.13 and 65-nm CMOS technology, respectively. The 65-nm CMOS filter implementation was also embedded into the I-branch of a single-chip 60-GHz dual-conversion receiver. Correspondingly, a third-order 1-GHz gm-C filter was designed for the Q-branch, rather as a test structure. The 1-GHz design is the third experimental gm-C filter circuit implemented in this work. All three filter implementations are original work in this book. Moreover, all of them were synthesized from lossy LC prototype filters in order to investigate and demonstrate the feasibility of the filter design approach presented in Chap. 4 and, especially, to benefit from the approach. The fifth-order 240-MHz gm-C filter implementations have previously been published in [1] and [2], respectively. The 1-GHz filter implementation has not been published because it did not function properly in the measurements, unlike the simulations. The second evolution version of the two WiMedia UWB receivers and the 60-GHz radio receiver, both implemented in a 65-nm CMOS technology, have been published in [3] and [4, 5], respectively. To the best of the authors’ knowledge, and based on [5], the latter is the first published 60-GHz radio receiver implementation that also contains an analog baseband circuit with an ADC on the same silicon chip with a 60-GHz receiver front-end. In the first evolution version of the two WiMedia UWB receivers, some re-design and, hence, re-processing needed to be done for the RF front-end and therefore, the first UWB receiver implementation has not been published as a complete RF receiver circuit. Instead, each individual circuit block has been published separately. This chapter is mainly based on the contents of the first four references of this chapter.