Lasse Aaltonen

A 2.2 mA 4.3 mm

The interface for a capacitive 2-axis micro-gyroscope is implemented in a 0.35-μm HVCMOS technology with a total area of 4.3 mm2. The ASIC comprises the complete analog interface electronics for the gyroscope, while the focus of the design is in maintaining low supply current and in reducing the chip area. The paper reports the design of reference circuits, high-voltage generation, drive-loop and the capacitive open-loop readout circuits. The prototype sensor that is measured is assembled by directly wire-bonding the stacked dies comprising the interface electronics and the sensor element. The noise floors of the two sensors are 0.028°/s/√{Hz} for z-axis and 0.032°/s/√{Hz} for y-axis. The supply current of the chip is 2.2 mA from a 3 V-supply.

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This paper investigates the sources of non-linearity of a self-balancing capacitive half-bridge sensor interface. It has been shown that the linearity of the interface output with respect to input acceleration is infinity at DC input signals when half-bridge sensor element is assumed as parallel plate capacitor pair. The linearity degrades as the input signal frequency gets higher. The source of the non-linearity is found out to be the phase difference between senor sensor element displacement and the interface output voltage. The analytical expression for the HD3 of the interface is derived. It has been seen that to increase the linearity of the interface, the phase difference can be decreased by increasing the cut-off frequency of the interface loop.

ASIC for a 1000

The interface for a capacitive 2-axis micro-gyroscope is implemented in a 0.35-μm HVCMOS technology with a total area of 4.3 mm2. The ASIC comprises the complete interface electronics for the gyroscope, while the focus of the design is in maintaining low supply current and in reducing the chip area. The core of the interface is the pseudo-continuous-time sense readout with an analog output, together with a continuous-time drive loop. The biasing and high-voltage generation will also be introduced in the paper. For the sensor that was implemented, the noise floors are 0.012 °/s/vHz for x-axis and 0.062 °/s/vHz for y-axis. The supply current of the chip is 2.2 mA from a 3 V-supply.

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As the complexity of the digital circuit blocks continues to increase, a power-on reset, POR, circuit is needed to initialize the digital logic to the known state at the start-up. This paper represents a POR with thresholds that are insensitive to the rise time of the supply voltage. This is achieved by generating the POR pulse with a constant current reference circuit. Moreover, current mirroring is used to improve hysteresis. The designed POR has a quiescent current of 3.1 µA (VDD=3.6 V) and operates with supplies ranging from 3 V to 3.6 V. The area of the circuit is 109.9 µm × 106.65 µm and the chip was implemented with triple-well 0.35 µm HVCMOS process.

/s 2-Axis Capacitive Micro-Gyroscope

This paper presents a differential SC second-order single-bit ΔΣ analog-to-digital converter (ADC). The converter has nominal conversion rate of 100 kS/s with OSR of 1000. Differential converter topology is used. This leads to lower second order harmonic and lower offset voltage compared to single ended topology. Together with SC implementation, the differential converter also makes it possible to use high impedance common mode reference voltages for low power operation. Chopper stabilization has been used to decrease offset and low frequency noise. The converter is designed and will be implemented in a 0.35 µm CMOS process with a total active area of 0.24 mm2. Typically, it consumes 60 µA from a 3.3 V supply.