T. Suemitsu

An analysis of the kink phenomena in InAlAs/InGaAs HEMT's using two-dimensional device simulation

Kink phenomena in InAlAs/InGaAs HEMTs are investigated using a two-dimensional (2-D) device simulation that takes into account impact ionization, including nonlocal field effects, and the surface states in a side-etched region at the gate periphery. The simulation model enables us to represent the kink, and it is found that the accumulation of holes generated by the impact ionization has the channel electron density in the side-etched region increase at the bias point where kink appears. When the electron density in the side-etched region is small, the hole accumulation causes a significant increase in that electron density, resulting in a large kink. The simulation results suggest a model in which the kink is described in terms of the modification of the parasitic source resistance induced by the hole accumulation. This model implies a way to eliminate the kink, that is, keeping the electron density in the side-etched region high.

30-nm two-step recess gate InP-Based InAlAs/InGaAs HEMTs

Two-step recess gate technology has been developed for sub-100-nm gate InP-based InAlAs/InGaAs high-electron mobility transistors (HEMTs). This gate structure is found to be advantageous for the preciseness of the metallurgical gate length as well as a comparable stability to the conventional gate structure with an InP etch stop layer. The two-step recess gate is optimized focusing on the lateral width of the gate recess. Due to the stability of the gate recess with an InP surface, a laterally wide gate recess gives the maximum cutoff frequency, lower gate leakage current, smaller output conductance and higher maximum frequency of oscillation. Finally, the uniformity of the device characteristics evaluated for sub-100-nm HEMTs with the optimized recess width. The result reveals the significant role of the short channel effects on the device uniformity.

30-nm-Gate InP-Based Lattice-Matched High Electron Mobility Transistors with 350 GHz Cutoff Frequency

The device characteristics and fabrication of 30-nm-gate InAlAs/InGaAs high electron mobility transistors (HEMTs) lattice-matched to InP substrates are reported. The gate length of 30 nm is achieved for a T-shaped gate geometry, which is necessary to minimize gate resistance for short-gate HEMTs, by using fullerene-incorporated nanocomposite resist in the electron beam direct writing of the bottom of the gate. In addition, the two-step-recess gate technology is used to minimize the extension of effective gate length. The devices provide excellent RF characteristics; a record cutoff frequency of 350 GHz is achieved.

30-nm-gate InAlAs/InGaAs HEMTs lattice-matched to InP substrates

In this paper, we report the fabrication and the device characteristics of the InP-based lattice-matched HEMTs with a 30-nm gate, which is the smallest gate yet achieved for InP-based HEMTs. A fullerene-incorporated nanocomposite resist is used in electron beam (EB) lithography to achieve such a small gate. A cutoff frequency of the 30-nm-gate HEMTs is 350 GHz, which is comparable to the reported value for 50-nm-gate InP-based pseudomorphic HEMTs and one of the highest value achieved by any kind of three-terminal electronic device.

Mechanism and structural dependence of kink phenomena in InAlAs/InGaAs HEMTs

The aim of this study is to find out the relationship between the kink and the structure of InAlAs/InGaAs HEMTs, or in other words, what the main parameters affecting the kink are. Two-dimensional device simulations were performed for this purpose, in which impact ionization and surface states were considered. For the impact ionization, an improved model which takes non-local effects into account was used for accurate estimation of ionization coefficients. The surface states in the side-etched region, expressed using a deep-level trap, were also necessary to represent the kink in the device simulation.

A 40-Gb/s Self-Clocked Bidirectional Serial/Parallel Converter for Asynchronous Label Swapping

A novel scheme for self-clocked bidirectional serial/parallel conversion is proposed with an optically clocked transistor array (OCTA). As a result of its internal clock generation, serial-to-parallel (SP) and parallel-to-serial (PS) conversion capability, the OCTA alone realizes a single-chip low-power interface between input-output high-speed asynchronous burst optical packets and complimentary metal-oxide-semiconductor electronics, thus enabling a compact low-power solution for label swapping of optical packets. An eight-channel OCTA demonstrates self-clocked SP and PS conversion at 40 Gb/s

Parasitic effects and long term stability of InP-based HEMTs

Abstract A study of InP based HEMTs implemented with different process options will be reported. It will be demonstrated that devices with an InP etch stopper layer or with a narrow lateral gate recess region do not present any kink effect, neither any transconductance frequency dispersion, g m (f) and a stable behavior with respect to hot electron aging is observed. The opposite occurs in devices without the InP etch stopper layer and a wide lateral gate recess region. The data presented confirm the effectiveness of an InP passivating layer in improving the reliability of advanced InP-HEMTs, and point out at the free InAlAs surface as responsible for the observed instabilities (kink effects, g m (f) dispersion).

Reliability study of parasitic source and drain resistances of InP-based HEMTs

The reliability of InP-based HEMTs is studied, focusing on how it is affected by the doped layer material and gate recess structure. Bias and temperature (BT) stress tests reveal that fluorine-induced donor passivation in the recess region, formed adjacent to the gate electrode, causes the source resistance (R/sub s/) to increase at large drain bias voltages. The increase in R/sub s/ can be prevented by using InP or InAlP as the carrier supply layer material instead of InAlAs. On the other hand, drain resistance (R/sub d/) increased due to carrier depletion in the drain ohmic region, which occurs not only in the recess region but also in the n/sup +/-capped region between the gate recess and the drain electrode, which is also affected by hot-carrier-induced damage.

Enhanced Gate Swing in InP HEMTs With High Threshold Voltage by Means of InAlAsSb Barrier

We demonstrated the suitability of the InP HEMTs with the InAlAsSb Schottky barrier to realize the high threshold voltage (enhancement mode), low gate current, and low power consumption. This quaternary compound material increases the conduction band discontinuity to the InGaAs channel by introducing only 10% of antimony to InAlAs. The gate current is reduced by an order of the magnitude (or even more) at gate voltage range from 0.4 to 0.8 V. On the other hand, the large conduction band discontinuity causes larger parasitic source and drain resistance, which decreases the extrinsic transconductance. Nevertheless, the high-frequency performance is comparable to the device with the conventional InAlAs barrier layer. Therefore, the InAlAsSb barrier is a promising option for logic applications, which requires reduced gate current. FETs, gate current, high-electron mobility transistors (HEMTs), high frequency.

An optically clocked transistor array (OCTA) for 40-Gb/s, bidirectional serial-to-parallel conversion of asynchronous burst optical packets

We have fabricated an optically clocked transistor array (OCTA) in an optoelectronic integrated circuit (OEIC) technology incorporating 0.18-µm gate length high-electron-mobility transistors (HEMTs). As a result of its dual serial-to-parallel (SP) and parallel-to-serial (PS) conversion (time demux/mux) capability, the OCTA realizes a single-chip, low-power interface between input/output high-speed asynchronous burst optical packets and CMOS electronics, thus enabling a compact, low-power solution for label swapping of optical packets. Single channel measurements indicate an input bandwidth greater than 65Gb/s. An eight-channel array demonstrates SP and PS conversion at 40Gb/s.