T. Torng

A Study of Write Margin of Spin Torque Transfer Magnetic Random Access Memory Technology

Key design parameters of 64 Mb STT-MRAM at 90-nm technology node are discussed. A design point was developed with adequate TMR for fast read operation, enough energy barrier for data retention and against read disturbs, a write voltage satisfying the long term reliability against dielectric breakdown and a write bit error rate below 10-9. A direct experimental method was developed to determine the data retention lifetime that avoids the discrepancy in the energy barrier values obtained with spin current- and field-driven switching measurements. Other parameters detrimental to write margins such as backhopping and the existence of a low breakdown population are discussed. At low bit-error regime, new phenomenon emerges, suggestive of a bifurcation of switching modes. The dependence of the bifurcated switching threshold on write pulse width, operating temperature, junction dimensions and external field were studied. These show bifurcated switching to be strongly influenced by thermal fluctuation related to the spatially inhomogeneous free layer magnetization. An external field along easy axis direction assisting switching was shown to be effective for significantly reducing the percentage of MTJs showing bifurcated switching.

High Spin Torque Efficiency of Magnetic Tunnel Junctions with MgO/CoFeB/MgO Free Layer

We present the results of a perpendicular magnetic tunnel junction (MTJ) that displays simultaneously low critical switching current and voltage, as well as high thermal stability factor. These results were achieved using a free layer of the MgO/CoFeB/MgO structure by increasing the spin torque efficiency to an average of 3.0 kBT/µA for 37-nm-diameter junctions, about three times that of a MgO/CoFeB/Ta free layer, which makes it the highest value reported to date. By comparing two films with different RA, hence different switching voltage and power, we explore the contributions of heating and voltage-modulated anisotropy change to the switching properties.

Fully functional perpendicular STT-MRAM macro embedded in 40 nm logic for energy-efficient IOT applications

We present for the first time a fully functional 40 nm perpendicular STT-MRAM macro (1 Mb, ×32/×64 IO) embedded into a foundry standard CMOS logic platform. We achieved target design specifications of 20 ns read access time and 20-100 ns write cycle time without redundancy repair at standard core and IO voltages. The full 1 Mb macro can be switched reliably with write pulse as short as 6 ns, which results in full-chip write power of ~ 3.2 μW/Mbps at ×64. This is the lowest eNVM write power reported at a full-chip level and about three orders of magnitude smaller than that of eFLASH. The 0.5 Mbit high-density bitcell array also demonstrates good Rp distribution and 100 % STT switching. Our results demonstrate superior power-area-feature attributes of perpendicular STT-MRAM as a best-in-class unified eNVM solution for Internet-of-Things (IOT) applications at 40 nm as well as the scalability of these advantages to 28 nm and beyond.

Study of dielectric breakdown distributions in magnetic tunneling junction with MgO barrier

The breakdown distribution of a magnetic tunnel junction (MTJ) with an ultrathin (∼1.2 nm) MgO barrier was studied, and two distinct distributions were identified. The breakdown distribution with high value demonstrates a wide peak-to-peak separation (∼13.4σ) to the critical spin torque induced switching voltage. However, the peak-to-peak separation is only ∼8.4σ for the devices showing low breakdown value. Both abrupt and gradual breakdown events were observed in two distributions. The dependence of the percentage of low breakdown devices as a function of bias polarity, test and stress conditions, MTJ film properties, and process conditions was investigated. The low breakdown percentage can be significantly reduced by increasing the RA value and MTJ process optimization.

5 Gb/in/sup 2/ recording with dual stripe AMR heads and low noise thin film disks

We have demonstrated magnetic recording at an areal density of 5 Gb/in/sup 2/ using dual stripe magnetoresistive heads (DSMR) on low noise and low-glide height quaternary CoCrTa-based alloy thin film disks. The data rate is 120 Mb/sec with a PR4 channel, and the on-track error rate achieved is around 10/sup -9/. The demonstration was accomplished in two cases using two different types of heads. In the first case, it was done with a DSMR head having shield-shield spacing of 0.165 /spl mu/m and 1 /spl mu/m stripe height flying at 25 nm, resulting in a linear density of 321.7 KBPI, and a track density of 15.6 KTPI. The second case was performed with DSMR heads having shield-shield spacing of 0.18 /spl mu/m and 8 /spl mu/m stripe height flying at proximity height of 12 nm, achieving a 358.75 KBPI and 13.8 KTPI. This is the highest linear density published so far for either GMR or AMR heads. It is the direct consequence of high signal/noise of DSMR heads and proximity recording over low noise, low-glide-height media. To explore the large dynamic range of DSMR heads, this study was also done with a variety of low noise disks with Mrt ranging broadly from 0.45 to 1.0 memu/cm/sup 2/ and coercivity of 3000 Oe.

High perpendicular anisotropy in sub-30 nm MRAM devices measured by spin-torque ferromagnetic resonance

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is the leading technology for next generation non-volatile embedded memories [1].

Development of STT-MRAM for embedded memory applications

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a leading candidate for embedded memory applications, with promises of low power, high performance, and non-volatility.

Spin Transfer Torque driven dynamics of the synthetic antiferromagnetic reference layer of perpendicular MRAM devices

Spin Transfer Torque Magnetic Random Access Memories (STT-MRAM) are based on Magnetic Tunnel Junctions (MTJs) made out of two ferromagnetic electrodes separated by a MgO tunnel barrier.

Perpendicular STT-MRAM for high speed non-volatile embedded memory application

The recent rise of mobile applications such as Internet of Things (IoT), wearable electronics, and context aware computing has renewed the search for a universal embedded memory technology [1]. Such a technology should combine fast read/write, low voltage operation, low power consumption, non-volatility, infinite endurance, with CMOS process compatibility. Magnetic Random Access Memory based on Spin Transfer Torque phenomena (STT-MRAM) has been recognized as a promising candidate. The technology is innately non-volatile, and it has been shown that STT-MRAM based on perpendicularly magnetized Magnetic Tunnel Junctions (MTJs) can be written at high speed with low power. However, two major challenges remain. The first is to design multilayered MTJs that can withstand temperatures used in CMOS backend processing without any degradation of their magnetic properties. The second challenge is that fast read/write must be achieved not only at the single device level, but on entire memory arrays which requires controlling defects and distributions of magnetic properties.

10 Gb/in/sup 2/ recording with DSMR AMR heads on low noise thin film disks

Areal density of 5 Gb/inz with AMR SAL was demonstrated[l] in the past, and more recently, with DSMR heads 121. Areal density of more than 10 Gb/in* with spin valve heads has been reported this yeafl5,SJ. However, in these demonstrations, there appears to have some practical weaknesses which make them unattractive for immediate practical applications. The details for the above spin valve heads has yet to be published but in one case [6]. using FIB write heads together with spin valve read heads is not yet practical. Here we will report 10 Gb/inz demonstration using dual stripe magneto-resistive heads [DSMR] with the current manufacturing process.