T. Zimmerman

The SVX4 integrated circuit

Abstract A first prototype of the SVX4 readout IC with enclosed transistor layout for radiation tolerance has been fabricated in a commercial 0.25 μm bulk CMOS process. The SVX4 is intended to instrument the CDF and D0 Run IIB silicon strip detector upgrades at Fermilab. The design and test results are discussed.

A fast, wide range charge integrator and encoder ASIC for photomultiplier tubes

A high-speed range pipelined integrator and encoder ASIC for fast digitization of charge from photomultiplier tubes is under development at Fermilab. The application-specific integrated circuit (ASIC) is intended to operate in conjunction with a fast analog-digital converter (ADC) to digitize signals from a charge source over a dynamic range of 18-20 b with 8-10 b of accuracy every 16 ns. Development of the device, called QIE (charge integrator and encoder), is being carried out in an IC process with CMOS and NPN devices. Many chips have been designed and tested to prove the feasibility of the device. >

Design of an advanced readout chip for silicon strip detectors

Work was begun in 1990 on the development of an advanced readout chip for silicon strip detectors. Features of the proposed device include compatibility with close bunch spacing and double sided detectors, and on-chip analog storage, digitization, and data sparsification. Chips have been designed to check all of these concepts, fabricated in the VTI 2 mu process, and tested. The circuit configurations and test results are presented. Measurements are very encouraging and show that performance is close to that desired. >

The SVX2 readout chip [Si strip detector]

A new readout chip called SVX2 is being designed for silicon detector systems at Fermilab. SVX2 is essentially an upgrade of the presently used SVX chip and contains extensive performance and feature enhancements. SVX2 is designed to accommodate much shorter beam crossing times (132 ns to 400 ns) with minimal increase in noise and power. Analog signal delay is formed by a double correlated sampling pipeline in order to allow time for trigger formation. Signal digitization of up to eight bits is performed on the chip with an A/D converter per channel. This allows threshold setting, sparsification, and readout to be purely digital. Design philosophy will be discussed and test results presented. >

The SVX2 readout chip

A new readout chip called SVX2 is being designed for silicon detector systems at Fermilab. SVX2 is essentially an upgrade of the presently used SVX chip and contains extensive performance and feature enhancements. SVX2 is designed to accommodate much shorter beam crossing times (132 ns to 400 ns) with minimal increase in noise and power. Analog signal delay is formed by a double correlated sampling pipeline in order to allow time for trigger formation. Signal digitization of up to eight bits is performed on the chip with an A/D converter per channel. This allows threshold setting, sparsification, and readout to be purely digital. Design philosophy is discussed and test results presented.<<ETX>>

Radioactive source calibration technique for the CMS hadron calorimeter

Abstract Relative calibration of the scintillator tiles used in the hadronic calorimeter for the Compact Muon Solenoid detector at the CERN Large Hadron Collider is established and maintained using a radioactive source technique. A movable source can be positioned remotely to illuminate each scintillator tile individually, and the resulting photo-detector current is measured to provide the relative calibration. The unique measurement technique described here makes use of the normal high-speed data acquisition system required for signal digitization at the 40 MHz collider frequency. The data paths for collider measurements and source measurements are then identical, and systematic uncertainties associated with having different signal paths are avoided. In this high-speed mode, the source signal is observed as a Poisson photo-electron distribution with a mean that is smaller than the width of the electronics noise (pedestal) distribution. We report demonstration of the technique using prototype electronics for the complete readout chain and show the typical response observed with a 144 channel test beam system. The electronics noise has a root-mean-square of 1.6 least counts, and a 1 mCi source produces a shift of the mean value of 0.1 least counts. Because of the speed of the data acquisition system, this shift can be measured to a statistical precision better than a fraction of a percent on a millisecond time scale. The result is reproducible to better than 2% over a time scale of 1 month.

Front end readout electronics for the CMS Hadron Calorimeter

The front-end electronics for the CMS Hadron Calorimeter provides digitized data at the beam interaction rate of 40 MHz. Analog signals provided by hybrid photodiodes (HPDs) or photomultiplier tubes (PMTs) are digitized and the data is sent off board through serialized fiber optic links running at 1600 Mbps. In order to maximize the input signal, the front-end electronics are housed on the detector in close proximity to the scintillating fibers or phototubes. To fit the electronics into available space, custom crates, backplanes and cooling methods have had to be developed. During the expected ten-year lifetime, the front-end readout electronics will exist in an environment where radiation levels approach 330 rads and the neutron fluence will be 1.3E11 n/cm/sup 2/. For this reason, the design approach relies heavily upon custom radiation tolerant ASICs. This paper will present the system architecture of the front-end readout crates and describe our results with early prototypes.