J. Hoff

Development of a pixel readout chip for BTeV

A description is given of the R&D program underway at Fermilab to develop a pixel readout ASIC appropriate for use at the Tevatron collider. Results are presentetd frOm tests performed on the first prototype pixel readout chip deigned at Fermilab, and a new readout architecture is described.

FPIX2: A radiation-hard pixel readout chip for BTeV

A radiation-hard pixel readout chip, FPIX2, is being developed at Fermilab for the recently approved BTeV experiment. Although designed for BTeV, this chip should also be appropriate for use by CDF and DZero. A short review of this development effort is presented. Particular attention is given to the circuit redesign which was made necessary by the decision to implement FPIX2 using a standard deep-submicron CMOS process rather than an explicitly radiation-hard CMOS technology, as originally planned. The results of initial tests of prototype 0.25{micro} CMOS devices are presented, as are plans for the balance of the development effort.

Calibration of a digital hadron calorimeter with muons

The calibration procedure of a finely granulated digital hadron calorimeter with Resistive Plate Chambers as active elements is described. Results obtained with a stack of nine layers exposed to muons from the Fermilab test beam are presented.The calibration procedure of a finely granulated digital hadron calorimeter with Resistive Plate Chambers as the active elements is described. Results obtained with a stack of nine layers exposed to muons from the Fermilab test beam are presented.

FSSR2, a self-triggered low noise readout chip for silicon strip detectors

The FSSR2 is the second release of the Fermilab Silicon Strip Readout Chip. The chip has been designed and fabricated in a 0.25 mum CMOS technology for high radiation tolerance. The first release, simply called the FSSR, was a prototype version with many different analog front-end configurations. The best solution was chosen for the FSSR2 chip to optimize the noise, according to criteria discussed in this paper. The FSSR2 has been designed for the silicon strip detectors of the BTeV experiment. The chip services 128 strips and provides address, time and magnitude information for all hits. Several programmable features are included in FSSR2, such as an internal pulser, a baseline restorer and a signal peaking time selectable among four values in the range between 65 ns and 125 ns. The circuit design and the performance of FSSR2 are discussed in this paper

30Mrad(SiO2) radiation tolerant pixel front end for the BTEV experiment

Abstract The FPIX project is an effort underway at Fermilab to develop a pixel detector ASIC appropriate for use in the BTEV experiment. The most ambitious aspect of this project is that all data from all hit pixels must be read out every beam crossing ( 132 ns ) for use in the lowest level trigger system. Included in each 50 μm ×400 μm pixel is a three-bit analog to digital converter which provides pulse height information to improve resolution. Given the proximity to the beam, the chips must be radiation tolerant. Rather than focusing efforts on a rad-hard technology, the choice has been made to use the inherent radiation tolerance of deep submicron processes with radiation tolerant design techniques. This paper discusses both the design and the radiation tolerance of the FPIX pixel cell.

The SVX4 integrated circuit

Abstract A first prototype of the SVX4 readout IC with enclosed transistor layout for radiation tolerance has been fabricated in a commercial 0.25 μm bulk CMOS process. The SVX4 is intended to instrument the CDF and D0 Run IIB silicon strip detector upgrades at Fermilab. The design and test results are discussed.

A fast, wide range charge integrator and encoder ASIC for photomultiplier tubes

A high-speed range pipelined integrator and encoder ASIC for fast digitization of charge from photomultiplier tubes is under development at Fermilab. The application-specific integrated circuit (ASIC) is intended to operate in conjunction with a fast analog-digital converter (ADC) to digitize signals from a charge source over a dynamic range of 18-20 b with 8-10 b of accuracy every 16 ns. Development of the device, called QIE (charge integrator and encoder), is being carried out in an IC process with CMOS and NPN devices. Many chips have been designed and tested to prove the feasibility of the device. >

Associative memory design for the fast track processor (FTK) at ATLAS

We propose a new generation of VLSI processors for pattern recognition, based on associative memory architecture, optimized for online track finding in high-energy physics experiments. We describe the architecture, the technology studies and the prototype design of a new associative memory project: it maximizes the pattern density on the ASIC, minimizes the power consumption and improves the functionality for the fast tracker processor proposed to upgrade the ATLAS trigger at LHC.

Analysis of full charge reconstruction algorithms for X-ray pixelated detectors

Existence of the natural diffusive spread of charge carriers on the course of their drift towards collecting electrodes in planar, segmented detectors results in a division of the original cloud of carriers between neighboring channels. This paper presents the analysis of algorithms, implementable with reasonable circuit resources, whose task is to prevent degradation of the detective quantum efficiency in highly granular, digital pixel detectors. The immediate motivation of the work is a photon science application requesting simultaneous timing spectroscopy and 2D position sensitivity. Leading edge discrimination, provided it can be freed from uncertainties associated with the charge sharing, is used for timing the events. Analyzed solutions can naturally be extended to the amplitude spectroscopy with pixel detectors

Lifetime Studies of 130 nm nMOS Transistors Intended for Long-Duration, Cryogenic High-Energy Physics Experiments

Future neutrino physics experiments intend to use unprecedented volumes of liquid argon to fill a time projection chamber in an underground facility. To increase performance, integrated readout electronics should work inside the cryostat. Due to the scale and cost associated with evacuating and filling the cryostat, the electronics will be unserviceable for the duration of the experiment. Therefore, the lifetimes of these circuits must be well in excess of 20 years. The principle mechanism for lifetime degradation of MOSFET devices and circuits operating at cryogenic temperatures is via hot carrier degradation. Choosing a process technology that is, as much as possible, immune to such degradation and developing design techniques to avoid exposure to such damage are the goals. This requires careful investigation and a basic understanding of the mechanisms that underlie hot carrier degradation and the secondary effects they cause in circuits. In this work, commercially available 130 nm nMOS transistors operating at cryogenic temperatures are investigated. The results show that the difference in lifetime for room temperature operation and cryogenic operation for this process are not great and the lifetimes at both 300 K and at 77 K can be projected to more than 20 years at the nominal voltage (1.5 V) for this technology.