Tadanori Yamaguchi

Analytical model and characterization of small geometry MOSFET's

Electrical characteristics of small geometry p-channel and n-channel MOSFETs are characterized based on an analytical model that includes short-channel, narrow-channel, and carrier-velocity-saturation effects. Theoretical results on threshold voltage, threshold-voltage shift by a substrate bias voltage, and drain current are in good agreement with the experimental results over wide ranges of channel lengths from 1 to 9 µm and channel widths from 2 to 14 µm. A comparison of the electrical characteristics of MOSFETs with and without field implantation leads to the conclusion that the field implantation is the main cause of the narrow-channel-width effect on threshold-voltage increase and drain-current degradation. The carrier-velocity-saturation effect starts to appear at the 3-µm channel length for the n-channel device and at 1 µm for the p-channel device under 5-V operation. According to the theoretical analysis of a 1-µm-channel inverter circuit, a CMOS inverter has superior noise immunity with 1.4 to 2.0 times larger driving-current capability in a load MOS device and requires 9 percent less area than a 1-µm n-channel enhancement/depletion inverter.

Process and device performance of a high-speed double poly-Si bipolar technology using borosenic-poly process with coupling-base implant

Use of boron and arsenic diffusions through an emitter polysilicon film (borosenic-poly emitter-base process) produces a transistor base width of less than 100nm with an emitter junction depth of 50 nm and an emitter-to-base reverse leakage current of approximately 70 pA. The borosenic-poly process resolves both the channeling and shadowing effects of a sidewall-oxided spacer during the base boron implantation. The process also minimizes crystal defects generated during the emitter and base implantations. The coupling-base boron implant significantly improves a wide variation in the emitter-to-collector periphery punchthrough voltage without degrading the emitter-to-base breakdown voltage current gain, cutoff frequency, or ECL gate delay time. A deep trench isolation with 4- mu m depth and 1.2- mu m width reduces the collector-to-substrate capacitance to 9 fF, while maintaining a transistor-to-transistor isolation voltage of greater than 25 V. The application of self-aligned titanium silicide technology to form polysilicon resistors without holes and to reduce the sheet resistance of the emitter and collector polysilicon electrodes to 1 Omega /square is discussed. >

Process integration and device performance of a submicrometer BiCMOS with 16-GHz f/sub t/ double poly-bipolar devices

Submicrometer-channel CMOS devices have been integrated with self-aligned double-polysilicon bipolar devices showing a cutoff frequency of 16 GHz. n-p-n bipolar transistors and p-channel MOSFETs were built in an n-type epitaxial layer on an n/sup +/ buried layer, and n-channel MOSFETs were built in a p-well on a p/sup +/ buried layer. Deep trenches with depths of 4 mu m and widths of 1 mu m isolated the n-p-n bipolar transistors and the n- and p-channel MOSFETs from each other. CMOS, BiCMOS, and bipolar ECL circuits were characterized and compared with each other in terms of circuit speed as a function of loading capacitance, power dissipation, and power supply voltage. The BiCMOS circuit showed a significant speed degradation and became slower than the CMOS circuit when the power supply voltage was reduced below 3.3 V. The bipolar ECL circuit maintained the highest speed, with a propagation delay time of 65 ps for C/sub L/=0 pF and 300 ps for C/sub L/=1.0 pF with a power dissipation of 8 mW per gate. The circuit speed improvements in the CMOS circuits as the effective channel lengths of the MOS devices were scaled from 0.8 to 0.4 mu m were maintained at almost the same ratio. >

Process and device design of a 1000-V MOS IC

High-voltage MOS devices and logic N-MOS circuits have been integrated on the same chip by using a silicon-gate isoplanar process that is compatible with present N-MOS LSI technology. The electrical characteristics of high-voltage MOS devices are modeled and characterized in terms of channel length, drift-layer length, drift-layer ion dose, and extended source field-plate effect. The theoretical calculations of on-resistanee, saturation drain current, and pinchoff voltage agree well with the experimental results. Based on the experimental and theoretical results, the device structure and the process parameters are optimized to obtain maximum drain saturation current with a low on-resistance and a drain breakdown of 1000 V. The optimized high-voltage MOS device can perform with a saturation drain current as high as 84 mA with an on-resistance as low as 300 Ω within an area of 520 µm × 1320 µm while maintaining a drain breakdown of 1000 V.

A dual 4-bit 2-Gs/s full Nyquist analog-to-digital converter using a 70-ps silicon bipolar technology with borosenic-poly process and coupling-base implant

A dual 4-b analog-to-digital converter (ADC) with Nyquist operation to 2 gigasamples/second (Gs/s) and -29-dBc distortion at 1 GHz is presented. A novel evaluation method using an integral digital-to-analog converter is introduced. A trench-isolated, self-aligned, double-polysilicon bipolar process is used for the chip fabrication. This ADC has a resolution of 3.73 effective bits at 1-GHz analog input signal, without the use of a preceding sample-and-hold. Low-frequency untrimmed distortion is -48 dBc (not including quantizing error), and is independent of the sample rate of 2 Gs/s. >

High-speed latchup-free 0.5-µm-channel CMOS using self-aligned TiSi 2 and deep-trench isolation technologies

A scaling study showed that a deeper n-well allows lower n-well surface concentration with improved short-channel effects in submicrometer-channel PMOS-FETs. However, the deep n-well leads to poor device-to-device isolation and to poor integration density. The deep-trench isolation combined with an epitaxial layer resolves this drawback and significantly improves Iatchup susceptibility. The sheet resistances of n+- and p+-diffusion and n+- doped polysilicon layers are reduced to 3-4ω/□ by using the self-aligned TiSi2layer with the oxide side-wall spacer. As a result of the deep-trench isolation combined with an epitaxial layer and the self-aligned TiSi2layer, the 0.5 µm-channel CMOS devices operated at a propagation delay time of 140 psec with a power dissipation of 1.5 mW per inverter and attained a maximum clock frequency of 400 MHz in a static ÷ 4 counter without suffering from latchup even at a latchup trigger current of 200 mA.

Process and device characterization for a 30-GHz f/sub T/ submicrometer double poly-Si bipolar technology using BF/sub 2/-implanted base with rapid thermal process

Process and device parameters are characterized in detail for a 30-GHz f/sub T/ submicrometer double poly-Si bipolar technology using a BF/sub 2/-implanted base with a rapid thermal annealing (RTA) process. Temperature ramping during the emitter poly-Si film deposition process minimizes interfacial oxide film growth. An emitter RTA process at 1050 degrees C for 30 s is required to achieve an acceptable emitter-base junction leakage current with an emitter resistance of 6.7*10/sup -7/ Omega -cm/sup 2/, while achieving an emitter junction depth of 50 nm with a base width of 82 nm. The primary transistor parameters and the tradeoffs between cutoff frequency and collector-to-emitter breakdown voltage are characterized as functions of base implant dose, pedestal collector implant dose, link-base implant dose, and epitaxial-layer thickness. Transistor geometry dependences of device characteristics are also studied. Based on the characterization results for poly-Si resistors, boron-doped p-type poly-Si resistors show significantly better performance in temperature coefficient and linearity than arsenic-doped n-type poly-Si resistors. >

Submicron bipolar-CMOS technology using 16 GHz f/sub T/ double poly-Si bipolar devices

Submicrometer CMOS devices were integrated with self-aligned double-polysilicon bipolar devices, showing a cutoff frequency of 16 GHz and an ECL circuit speed of 65 ps/gate. It was found that an amorphous silicon film deposited at 575 degrees C and used as the base electrode improve the gate oxide breakdown voltage compared to a polysilicon film deposited at 600 degrees C. The PMOS FETs showed good short-channel behavior for effective channel lengths down to 0.6 mu m, while the NMOS FETs showed a hump in subthreshold current. This hump was eliminated by minimizing the overetch during the base polysilicon reactive-ion-etching process. Minimum-cell CMOS, BiCMOS and bipolar ECL (emitter-coupled logic) circuits were characterized as functions of loading capacitance, power dissipation, power supply voltage, and channel length of the MOS devices. The relative circuit speed improvements in the BiCMOS and CMOS circuits as the channel lengths were scaled from 0.8 mu m to 0.4 mu m were almost the same, while the BiCMOS circuit speed became slower than that of the CMOS when the power supply voltage was reduced below 3.3 V.<<ETX>>

Process and device performance of submicrometer-channel CMOS devices using deep-trench isolation and self-aligned TiSi 2 technologies

According to our scaling study, a deeper n-well allows for a lower n-well surface concentration with improved short-channel effects in submicrometer-channel PMOS-FETs. The deep n-well, however, requires a large space between n- and p-channel devices. This large space limits the integration density in scaled bulk CMOS VLSIs. The deep-trench isolation combined with an epitaxial layer resolves this drawback with significantly improved device-to-device isolation and latchup susceptibility. The 6-µm-deep with 2-µm-wide deep trench is etched in the epitaxial layer and is refilled with 1500 A of thermal silicon-dioxide film and 2 µm of polysilicon film. The sheet resistances of N+and P+diffusion and N+-doped polysilicon layers were reduced to 3 to 4 Ω/□ by using the self-aligned TiSi 2 layer with an oxide sidewall spacer. As a result of this low sheet resistance, the saturation drain current of submicrometer n- and p-channel MOSFETs was improved approximately 33 to 37 percent compared with conventional MOSFETs without the self-aligned TiSi 2 layer. The 0.5-µm-channel CMOS devices using the deep-trench isolation with an epitaxial layer and the self-aligned TiSi 2 layer operated at a propagation delay time of 140 ps with a power dissipation of 1.1 mW per inverter and attained a maximum clock frequency of 400 MHz in a static / 4 counter without suffering from latchup even at the latchup trigger current of 200 mA.

An advanced MOS-IC process technology using local oxidation ot oxygen-doped polysilicon films

An O-POS (oxygen-doped polysilicon) film, deposited directly on silicon, is oxidized locally to create an active gate area. The electrical properties for the active gate area are the same as conventional p- and n-channel MOS devices, but the field area has an extremely high threshold voltage for both p- and n-type silicon substrates. The electrical properties in metal/oxidized O-POS/silicon and metal/oxide/O-POS/silicon structures have been investigated while varying the O-POS film thickness, oxygen concentration, local oxidation time, and silicon substrate resistivity. According to these basic studies, it is proposed that the high density of trapping centers existing in O-POS film is responsible for the high field threshold voltage. A applications of this process technology, a silicon-gate CMOS integrated circuit, and a high voltage n-channel MOS device are discussed.