Tae-Ho Hwang

A Fully CMOS Integrated RF Transceiver for Ubiquitous Networks in Sub-GHz ISM-band

A fully CMOS integrated radio frequency (RF) transceiver for wireless sensor networks in sub-GHz ISM-band applications is implemented and measured. The IC is fabricated in 0.18-mum CMOS technology and packaged in LPCC package. The fully monolithic transceiver consists of a receiver, a transmitter and a RF synthesizer with on-chip VCO. The chip fully complies with the IEEE 802.15.4 WPAN standard in sub-GHz mode. The receiver sensitivity is -98 dBm and the transmitter achieves less than 6.3% error vector magnitude (EVM) for 40 kbps mode. The chip uses 1.8 V power supply and the current consumption is 14 mA for reception mode ad 16 mA for transmission mode

Implementation of Implantable Cardioverter Defibrillator

In this paper, we implement Implantable Cardioverter Defibrillator (ICD) system. In order to implement the ICD, we propose the baseband according to modulation method, modulation index and bandwidth time product. From simulation results, we decide GFSK modulation with modulation index 0.2 and bandwidth time product 0.5. Also the receiver sensitivity of ICD link budget decides −83.22dBm using receiver antenna gain, receiver power and noise figure. In test and verification of implemented SoC prototype, we obtain the packet error rate 1% at −83dBm.

A Fully Integrated SoC with Digital MAC Processor and Transceiver for Ubiquitous Sensor Network at 868/915 MHz

SUMMARY A single-chip ubiquitous sensor network (USN) systemon-a-chip (SoC) for small program memory size and low power has been proposed and integrated in a 0.18-µm CMOS technology. Proposed singlechip USN SoC is mainly consists of radio for 868/915 MHz, analog building block, complete digital baseband physical layer (PHY) and media access control (MAC) functions. The transceiver’s analog building block includes a low-noise amplifier, mixer, channel filter, receiver signal-strength indication, frequency synthesizer, voltage-controlled oscillator, and power amplifier. In addition, digital building block consists of differential binary phase-shift keying (DPSK) modulation, demodulation, carrier frequency offset compensation, auto-gain control, embedded 8-bit microcontroller, and digital MAC function. Digital MAC function supports 128 bit advanced encryption standard (AES), cyclic redundancy check (CRC), intersymbol timing check, MAC frame control, and automatic retransmission. These digital MAC functions reduce the processing power requirements of embedded microcontroller and program memory size by up to 56%. The cascaded noise figure and sensitivity of the overall receiver are 9.5 dB and −99 dBm, respectively. The overall transmitter achieves less than 6.3% error vector magnitude (EVM). The current consumption is 14 mA for reception mode and 16 mA for transmission mode.

Implementation of a low-overhead processing-in-memory architecture

Since the new technologies like big data and cloud computing require tremendous amount of transactions between CPU and memory, researches on a new memory system called PIM (processing in memory) architecture has been suggested as a solution for those memory intensive applications. This paper introduces a low-head PIM architecture. And we introduce the processing techniques of the PIMs instructions on the PIM architecture. And we have designed the PIM architecture using Verilog HDL, and the operation of the PIM architecture verified through RTL simulation.

A CMOS continuous-time Gm-C filter and programmable gain amplifier for WPAN receivers

This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable-gain amplifier (PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve low current consumption. High linearity and constant wide bandwidth are achieved by using a new transconductance (Gm) cell. The PGA has a voltage gain varying from 0 to 65dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. With a 1-Vrms differential input and output, the filter achieves -85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA were implemented in a 0.18mum 1P6M n-well CMOS process. They consume 3.2mW from a 1.8V power supply and occupy an area of 0.19mm2