Taha Beyrouthy

Physical Design of FPGA Interconnect to Prevent Information Leakage

In this article we discuss dual/multi-rail routing techniques in an island style FPGA for robustness against side-channel attacks. We present a technique to achieve dual-rail routing balanced in both timing and power consumption with the traditional subset switchbox. Secondly, we propose two switchboxes (namely: Twist-on-Turn & Twist-Always) to route every dual/multi-rail signal in twisted pairs, which can deter electromagnetic attacks. These novel switchboxes can also be balanced in power consumption albeit with some added cost. We present a layout with pre-placed switches and pre-routed balanced wires and extraction statistics about the expected balance. As conclusion, we discuss various overheads associated with these techniques and possible improvements.

An event-driven FIR filter: Design and implementation

Non-uniform sampling has proven through different works, to be a better scheme than the uniform sampling to sample low activity signals. With such signals, it generates fewer samples, which means less data to process and lower power consumption. In addition, it is well-known that asynchronous logic is a low power technology. This paper deals with the coupling between a non-uniform sampling scheme and an asynchronous design in order to implement a digital Filter. This paper presents the first design of a micropipeline asynchronous FIR filter architecture coupled to a non-uniform sampling scheme. The implementation has been done on an Altera FPGA board.

A Novel Asynchronous e-FPGA Architecture for Security Applications

With the growing security needs of applications such as homeland security or banking, the frequent updates in cryptographic standards and the high ASIC costs, the ciphering algorithms on an asynchronous embedded FPGA co-processor are becoming a viable alternative. Within the SAFE project, a novel architecture of asynchronous e-FPGA has been proposed. This architecture is natively robust against side channel attacks such as simple and differential power analysis or clock based fault attacks. Simulation-based security proofs are also presented.

Data sampling and processing: Uniform vs. non-uniform schemes

It has been shown in previous works that non-uniform sampling and processing is a better scheme than the uniform sampling to sample and process low activity signals. Non-uniform sampling technique generates fewer samples, which means less data to process and lower power consumption. Furthermore, asynchronous logic is known to be data-driven. It proves to be more adapted to the non-uniform sampling than synchronous logic. It is thus a better alternative to design low power data-processing circuits. In this paper, we present an overview of the non-uniform sampling scheme. It also describes the architectures of a processing function (Finite Impulse Response filter) in synchronous and asynchronous technologies. These circuits have been implemented on an Altera EP2C8 FPGA in order to extract and compare their activities profiles.

Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks

Cryptographic circuits are subject to sneak attacks that target directly their implementation. So-called side-channel analyses consist in observing dynamic circuit emanations in order to derive information about the secrets it conceals. Clock-less logic styles natively make side-channel attacks difficult, because of the absence of timing references for the algorithm beginning or ending. We present two ways to implement secure clock-less cryptographic circuits. The first one is based on a local synchronization at the gate level, and helps achieving close to constant emanations. The second one is more audacious as it is based merely on removing all synchronization. This approach proves to be very promising in terms of protection against side-channel attacks, while keeping a reasonable overhead both in terms of cost and performance.

An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications

This paper presents an FPGA tech-mapping algorithm dedicated to security applications. The objective is to implement—on a full-custom asynchronous FPGA—secured functions that need to be robust against side-channel attacks (SCAs). The paper briefly describes the architecture of this FPGA that has been designed and prototyped in CMOS 65 nm to target various styles of asynchronous logic including 2-phase and 4-phase communication protocols and 1-of-n data encoding. This programmable architecture is designed to be electrically balanced in order to fit the security requirements. It allows fair comparisons between different styles of asynchronous implementations. In order to illustrate the FPGA flexibility and security, a case study has been implemented in 2-phase and 4-phase Quasi-Delay-Insensitive (QDI) logic.