Taher Daud

Charge-Coupled-Device Response To Electron Beam Energies Of Less Than 1 keV up to 20 keV

Recent developments of backside treatment for the backside-illuminated scientific charge-coupled device (CCD) imagers have shown near-theoretical efficiency even at the short wavelength region of the spectrum. By using a scanning electron microscope (SEM), we report here, for the first time, performance comparisons of backside-treated and untreated CCDs to an electron flux varying from 1 to 100 pA and beam energy ranging from less than 1 keV up to 20 keV. We describe the theoretical analysis, the SEM testing procedure, and the quantum efficiency measurement results. It is shown, for example, that the average quantum efficiency increases from less than 1% for an untreated CCD to nearly 40% for a backside-treated CCD at a beam energy of 1 keV.

CCD Advances For X-Ray Scientific Measurements In 1985

A theoretical model is presented which predicts the output response of a CCD to soft X-ray spectra. The model simulates the four fundamental parameters that ultimately limit CCD performance: Quantum efficiency, charge collection efficiency, charge transfer efficiency, and read noise. Simulated results are presented for a wide variety of CCD structures, and general conclusions are presented about achieving a practical balance of sensitivity, energy, and spatial resolution for an AXAF instrument. We compare the results of the analysis to an existing state-of-the-art CCD and project improvements which will be made in the near future.

Evolutionary recovery of electronic circuits from radiation induced faults

Radiation hard technologies for electronics are the conventional approach for survivability in high radiation environments. This work presents a novel approach based on evolvable hardware. The key idea is to reconfigure a programmable device, in-situ, to compensate, or bypass its degraded or damaged components. The paper demonstrates the approach using a JPL-developed reconfigurable device, a field programmable transistor array (FPTA), which shows recovery from radiation damage when reconfigured under the control of evolutionary algorithms. Experiments with total radiation dose up to 350kRad show that while the functionality of a variety of circuits, including a rectifier and a digital to analog converter implemented on a FPTA-2 chip, is degraded/lost at levels before l00KRad, the correct functionality can be recovered through the proposed evolutionary approach. The evolutionary algorithm controls the state of about 1,500 switches that determine configurations on the FPTA-2 programmable device. Evolution is able to use the resources of the reconfigurable cells, even radiation damaged components, to synthesize a new solution.

The CCD Flash Gate

Preliminary findings are presented for a new approach that significantly improves the quantum efficiency of the current generation of high-performance, thinned, backside illuminated silicon CCDs. Experiments have shown that the application of an ultra-thin (less than 4a) layer of metal with high work function to the backside of the CCD can yield 100% internal quantum efficiency in the visible, UV, XUV and soft X-ray regions of the spectrum. Theory and solid state models describing the new technique (which we refer to as the CCD flash gate), plus a considerable amount of experimental data are discussed in this paper. Specific recommendations for use of the flash gate in present and future CODs are also reviewed.

Progress in the Development of Field Programmable Analog Arrays for Space Applications

Development of analog electronic solutions for space avionics is expensive and lengthy. Lack of flexible analog devices, counterparts to digital field programmable gate arrays (FPGA), prevents analog designers from benefits of rapid prototyping. This forces them to expensive and lengthy custom design, fabrication, and qualification of application specific integrated circuits (ASIC). The limitations come from two directions: first, commercial field programmable analog arrays (FPAA) have very limited variability in the components offered on-chip (practically one type of operational amplifiers/comparator per chip); and second, these are only qualified for best case scenarios for military grade (-55degC to +125degC). However, analog circuitry required for sensing and control involves a larger variability. Moreover, in order to avoid huge overheads in mass, energy and wiring, there is a growing trend towards avoiding thermal and radiation protection by developing extreme environment electronics. This means electronics that maintain correct operation while exposed to temperature extremes e.g., on Moon (-180degC to +125degC). This paper describes a recent FPAA design, the self-reconfigurable analog array (SRAA) that was developed at JPL. It overcomes both limitations, offering a variety of analog cells inside the array together with the possibility of self-correction at extreme temperatures.

High-resolution synaptic weights and hardware-in-the-loop learning

Artificial neural network paradigms are derived from biological nervous system and are characterized by massive parallelism. These networks have shown the capabilities of processing input-output mapping operations even where the transformation rules are not known, partially known, or ill-defined. For high-speed processing, we have fabricated neural network architectures as building-block chips with either a 32 X 32 matrix of synapses or a 32 X 31 array of synapses along with 32 neurons along a diagonal for a 32 X 32 matrix. Reconfigurability allows a variety of architectures from fully recurrent to fully feedforward, including constructive architectures such as cascade correlation. Further, a variety of gradient-descent learning algorithms have been implemented. Additionally, the chips being cascadable, larger size networks are easily assembled. An innovative scheme of combining two identical synapses on two respective chips in parallel nominally doubles the bit resolution from 7 bits (6-bit + sign) to 13 bits (12-bit + sign). We describe the feedforward net obtained by assembly of 8 chips on a board with nominally 13 bits of resolution for a hardware-in-the-loop learning of a feature classification problem involving map-data. This neural net hardware with 27 analog inputs and 7 outputs is able to learn to classify the features and provide the required output map at high speed with 89% accuracy. This result, with hardwares lower precision, etc., compares favorably with an accuracy of 92% obtained both by a neural network software simulation (floating point accuracy of synaptic weights) and a statistical technique of k-nearest neighbors.

Self-Reconfigurable Analog Array Integrated Circuit Architecture for Space Applications

Development of analog electronics solutions for space avionics is expensive and time-consuming. Lack of flexible analog devices, counterparts to digital Field Programmable Gate Arrays (FPGA), prevents analog designers from the benefits of rapid prototyping. This forces them to expensive and lengthy custom design, fabrication, and qualification of application specific integrated circuits (ASIC). The limitations come from two directions: first, commercial Field Programmable Analog Arrays (FPAA) have very limited variability in the building block components offered on-chip (practically only one type of operational amplifiers/ comparator per chip); and second, these are only qualified for best case scenarios for military grade (-55degC to +125degC). However, the analog circuitry required for sensing and control impose a larger component variability. Moreover, in order to avoid large overheads in mass, energy and wiring, there is a growing trend towards avoiding thermal and radiation protection by developing extreme environment electronics, i.e. electronics that maintain correct operation while directly exposed to temperature extremes e.g., on Moon (-180degC to +125degC). This paper describes a recent FPAA design, the Self-Reconfigurable Analog Array (SRAA) that was developed at JPL. It overcomes both limitations: a larger variety of analog building block components in the cells of the array and the possibility to operate over a wide range by compensating deviations due to temperature using a built in general purpose genetic algorithm (GA) engine as an IP core.

Flash Technology for CCD Imaging in the UV

The introduction of the flash gate has made possible the fabrication of backside-illuminated CCDs with high sensitiv4y and stability throughout a wide range of ultraviolet and visible wavelengths (100-5000 Å). It has been determined that the characteristics of the oxide layer beneath the gate are critical to the ultimate performance that can be achieved. By creating an improved oxide layer in conjunction with the flash gate, we are now able to consistently produce CCDs with near-ideal UV performance. In the interest of transferring flash technology to industry, we present in this paper recent results and related background theory that optimize the flash gate specifically for application in the UV.

VIGILANTE: an advanced sensing/processing testbed for ATR applications

VIGILANTE consists of two major components: (1) the viewing image/gimballed instrumentation laboratory (VIGIL) -- advanced infrared, visible, and ultraviolet sensors with appropriate optics and camera electronics; (2) the analog neural three- dimensional processing experiment (ANTE) -- a massively parallel, neural network-based, high-speed processor. The powerful combination of VIGIL and ANTE will provide real-time target recognition/tracking capability suitable for ballistic missile defense organization (BMDO) applications as well as a host of other civil and military uses. In this paper, we describe VIGILANTE and its application to typical automatic target recognition (ATR) applications (e.g., aircraft/missile detection, classification, and tracking), this includes a discussion of the VIGILANTE architecture with its unusual blend of experimental 3D electronic circuitry, custom design and commercial parallel processing components, as well as VIGILANTEs ability to handle a wide variety of algorithms which make extensive use of convolutions and neural networks. Our paper also presents examples and numerical results.

Evolutionary configuration of field programmable analog devices

The purpose of this paper is to illustrate evolution of analog circuits on a stand-alone board-level evolvable system (SABLES). SABLES is part of an effort to achieve integrated evolvable systems. SABLES provides autonomous, fast (tens to hundreds of seconds), on-chip circuit reconfiguration. Its main components are a JPL Reconfiguration Mecltanism: Evolutionary Processor Supercomputer, PCICPU -DSP, FPGA, ASIC H Reconfigurable Hardware Unconstrained (model in SPICE) FPGA (Xilinx chips) FPAA (model, Lattice) FPTA (model, chips)