Anilkumar P. Thakoor

Competitive neural architecture for hardware solution to the assignment problem

Abstract A neural network architecture for competitive assignment is presented, with details of a very large scale integration (VLSI) design and characterization of critical circuits fabricated in complementary metal-oxide semiconductor (CMOS). The assignment problem requires that elements of two sets (e.g., resources and consumers) be associated with each other such as to minimize the total cost of the associations. Unlike previous neural implementations, association costs are applied locally to processing units (PUs, i.e., neurons), reducing connectivity to VLSI-compatible O(number of PUs). Also, each element in either set may be independently programmed to associate with one, several, or a range of elements of the other set. A novel method of “hysteretic annealing,” effected by gradually increasing positive feedback within each PU, was developed and compared in simulations to mean-field annealing implemented by increasing PU gain over time. The simulations (to size 64 × 64) consistently found optimal or near-optimal solutions, with settling times of about 150 microseconds, except for a few variable-gain annealing trials that exhibited oscillation.

Solid‐state thin‐film memistor for electronic neural networks

We report on a tungsten‐oxide‐based, nonvolatile, electrically reprogrammable, variable resistance device as an analog synaptic memory connection for electronic neural networks. A voltage controlled, reversible injection of H+ ions in electrochromic thin films of WO3 is utilized to modulate its resistance. A hygroscopic thin film of Cr2 O3 is the source of H+ ions. The resistance of the device can be tailored and stabilized over a wide dynamic range (∼four orders of magnitude), and the programming speed is modulated by the control voltage. The suitability of such a device in terms of its response speed, reversibility, stability, and cyclability for its use in electronic neural networks is discussed.

Electronic hardware implementations of neural networks

This paper examines some of the present work on the development of electronic neural network hardware. In particular, the investigations currently under way at JPL on neural network hardware implementations based on custom very large scale integrated technology, novel thin film materials, and an analog-digital hybrid architecture are reviewed. The availability of such hardware will greatly benefit and enhance the present intense research effort on the potential computational capabilities of highly parallel systems based on neural network models.

High Tc superconducting NbN films deposited at room temperature

Thin films of niobium nitride with superconducting transition temperature (Tc ) of 15.7 K have been deposited on a variety of amorphous as well as crystalline substrates including glass, glazed ceramic, fused quartz, and sapphire, maintained at room temperature, by dc reactive magnetron sputtering in a mixture of Ar and N2 gases. The effects of the deposition conditions, particularly the carrier gas pressure and composition, on the film crystal structure, orientation, and resistivity have been studied in an effort to maximize the superconducting transition temperature. A study of the variation of nitrogen consumption with nitrogen injection pressures for constant background argon pressures is conducted and found to be an absolute indicator of the NbN formation systematics. Initially, the consumption increases linearly with the injection pressure but beyond a certain threshold, it shows a distinct drop. The desired high Tc  NbN with B1 crystal structure is formed in the vicinity of this turning point of th...

Analog VLSI neural networks: implementation issues and examples in optimization and supervised learning

Time-critical neural network applications that require fully parallel hardware implementations for maximal throughput are considered. The rich array of technologies that are being pursued is surveyed, and the analog CMOS VLSI medium approach is focused on. This medium is messy in that limited dynamic range, offset voltages, and noise sources all reduce precision. The authors examine how neural networks can be directly implemented in analog VLSI, giving examples of approaches that have been pursued to date. Two important application areas are highlighted: optimization, because neural hardware may offer a speed advantage of orders of magnitude over other methods; and supervised learning, because of the widespread use and generality of gradient-descent learning algorithms as applied to feedforward networks. >

Low power analog neurosynapse chips for a 3-D "sugarcube" neuroprocessor

Object discrimination and pattern recognition are computationally intensive and for many defense and commercial applications, speed is of the essence. A novel 3-dimensional VLSI architecture in which neural network integrated circuits (ICs) are stacked together and mated to an image sensor may be used to solve such problems. New compact, high speed, low power, analog neuron and synapse circuits, suitable for such 3-D z-plane stacking are reported. The neural circuits have been designed for incorporation into a reconfigurable multilayer perceptron consisting of 64 inputs, up to 64 hidden units, and up to 6 outputs, which can be utilized to solve a variety of pattern recognition problems. The circuits, fabricated in a 1.2 /spl mu/m CMOS process have achieved 125 ns propagation through a synapse neuron pair, resulting in 4 MHz operation through the envisioned 3 layer feed forward network. Power dissipation at these speeds is expected to be under 30 mW per chip.<<ETX>>

Insulator interface effects in sputter-deposited NbN/MgO/NbN (superconductor--insulator--superconductor) tunnel junctions

All refractory, NbN/MgO/NbN (superconductor–insulator–superconductor) tunnel junctions have been fabricated by in situ sputter deposition. The influence of MgO thickness (0.8–6.0 nm) deposited under different sputtering ambients at various deposition rates on current–voltage (I–V) characteristics of small‐area (30×30 μm) tunnel junctions is studied. The NbN/MgO/NbN trilayer is deposited in situ by dc reactive magnetron (NbN), and rf magnetron (MgO) sputtering, followed by thermal evaporation of a protective Au cap. Subsequent photolithography, reactive ion etching, planarization, and top contact (Pb/Ag) deposition completes the junction structure. Normal resistance of the junctions with MgO deposited in Ar or Ar and N2 mixture shows good exponential dependence on the MgO thickness indicating formation of a pin‐hole‐free uniform barrier layer. Further, a postdeposition in situ oxygen plasma treatment of the MgO layer increases the junction resistance sharply, and reduces the subgap leakage. A possible enrichment of the MgO layer stoichiometry by the oxygen plasma treatment is suggested. A sumgap as high as 5.7 mV is observed for such a junction

Refractory amorphous metallic (W0.6Re0.4)76B24 coatings on steel substrates

Refractory metallic coatings of (W0.6Re0.4)76B24 (WReB) have been deposited onto glass, quartz, and heat-treated AISI 52100 bearing steel substrates by dc magnetron sputtering. As-deposited WReB films are amorphous, as shown by their diffuse x-ray diffraction patterns; chemically homogeneous, according to secondary ion mass spectrometry (SIMS) analysis; and they exhibit a very high (~1000°C) crystallization temperature. Adhesion strength of these coatings on heat-treated AISI 52100 steel is in excess of ~20, 000 psi and they possess high microhardness (~2400 HV50). Unlubricated wear resistance of such hard and adherent amorphous metallic coatings on AISI 52100 steel is studied using the pin-on-disc method under various loading conditions. Amorphous metallic WReB coatings, about 4 µm thick, exhibit an improvement of more than two and a half orders of magnitude in the unlubricated wear resistance over that of the uncoated AISI 52100 steel.

Learning and optimization with cascaded VLSI neural network building-block chips

To demonstrate the versatility of the building-block approach, two neural network applications were implemented on cascaded analog VLSI chips. Weights were implemented using 7-b multiplying digital-to-analog converter synapse circuits, with 31*32 and 32*32 synapses per chip. A novel learning algorithm compatible with analog VLSI was applied to the two-input parity problem. The algorithm combines dynamically evolving architecture with limited gradient-descent backpropagation for efficient and versatile supervised learning. To implement the learning algorithm in hardware, synapse circuits were paralleled for additional quantization levels. The hardware-in-the-loop learning system allocated 2-5 hidden neurons for parity problems. Also, a 7*7 assignment problem was mapped onto a cascaded 64-neuron fully connected feedback network. In 100 randomly selected problems, the network found optimal or good solutions in most cases, with settling times in the range of 7-100 mu s.<<ETX>>

Room temperature deposition of superconducting NbN for superconductor–insulator–superconductor junctions

Reactive dc magnetron sputtering is used to deposit hard, refractory, superconducting thin films of niobium nitride on amorphous (glass) as well as crystalline (sapphire) substrates held at room temperature. Stoichiometric NbN films so obtained possess the desired B1 crystal structure with a distinct (111) texture, and exhibit high (∼16 K) superconducting transition temperature. Room temperature deposition of the high Tc films is achieved primarily by optimizing the reactant fluxes of niobium and nitrogen reaching the substrate, through a systematic study of the nitrogen consumption versus injection characteristics which are found to be an absolute indicator of the quality of NbN formed. Superconductor–insulator–superconductor (SIS) junctions are fabricated by using high Tc NbN as the base electrode, a thin layer of native oxide grown in oxygen plasma or in room air as the insulator, and vacuum deposited Pb as the counterelectrode. The current versus voltage (I–V) characteristics of the junctions exhibit ...