Tai Haur Kuo

A wideband CMOS sigma-delta modulator with incremental data weighted averaging

A low-complexity high-speed circuit is proposed for the implementation of an incremental data weighted averaging (IDWA) technique used for reducing digital-to-analog converter (DAC) noise due to component mismatches. IDWA can achieve very good performance even when it is used with a low oversampling ratio (OSR), which reduces demands on circuit speed and power consumption. Therefore, the IDWA is highly suitable for wideband, low-power and small-area sigma-delta modulator (SDM) implementation. Incorporating the IDWA technique, a fourth-order feedforward (FF) SDM with an OSR of 12 and a 4-bit internal quantizer is implemented with a 2.5-V 0.25-/spl mu/m CMOS process. Measurement results show that the SDM operating from a 2.5-V supply voltage can achieve respective dynamic ranges (DRs) of 84/80 dB and spurious-free dynamic ranges (SFDRs) of 90/85 dB with signal bandwidths of 1.25/2 MHz at sampling frequencies of 30/48 MHz. The power dissipation is less than 105 mW and the active area is 2.6 mm/sup 2/. Wider bandwidth, lower OSR, less power, and lower supply voltage are achieved compared with two recently published 3.3-V/3-V CMOS wideband SDMs with comparable SNDR performance.

Automatic coefficients design for high-order sigma-delta modulators

An automatic-design methodology for designing high-tolerance modulator coefficients for high-order sigma-delta modulators (SDMs) from system specifications is presented. The methodology covers many design concerns including SDM coefficient tolerances for circuit component mismatch, stability, reduction of in-band tones, design tradeoffs among in-band noise suppression, oversampling ratio, and modulator order. Moreover, a high-order SDM synthesis tool (HOST) based on the methodology has been implemented in a C language program. Even for inexperienced designers, reliable and high-tolerance SDM coefficients for various applications can be automatically and efficiently generated using HOST. For synthesized SDMs with orders from three to eight and oversampling ratios from 32 to 256, coefficient variations within 2% (1% for the eighth order) are allowed and the resulting peak signal-to-noise ratio degradation is less than 3 dB. Several design examples synthesized by HOST are included.

A novel A/D converter using resonant tunneling diodes

A large-signal resonant tunneling diode (RTD) model is used to simulate the performance of a 2-b A/D converter. Results from the theoretical analysis, the breadboard circuit demonstration, and the SPICE3 simulation are discussed. It is shown that the unique folding characteristics of the vertically integrated RTD greatly reduce the complexity of the A/D converter circuit, making analog-to-digital conversion at tens-of-gigahertz rates possible. >

An improved technique for reducing baseband tones in sigma-delta modulators employing data weighted averaging algorithm without adding dither

The data weighted averaging (DWA) algorithm used in multibit sigma-delta modulators (SDM) is troubled by baseband tones resulting from component mismatch of the SDMs internal multi-bit digital-to-analog converter (DAC). In this paper, we analyze DAC baseband tones and find them closely correlated to the number of unit elements used in the DAC. An improved technique is proposed for shifting the DAC tones away from the baseband without adding dither. For third-order sigma-delta modulators with an oversampling ratio (OSR) of 64 and either a nine-level or eight-level internal DAC with 0.5%-2% random component mismatches, simulation reveals that the DWA algorithm with the proposed technique can achieve nearly perfect first-order DAC noise shaping in the baseband and, on the average, 12 dB improved signal-to-(noise and distortion) ratio and 20 dB improved in-band distortion.

Large-signal resonant tunneling diode model for SPICE3 simulation

The I-V characteristics of a multipeak resonant tunneling diode (RTD) are analyzed. A large signal model is developed so that the multipeak RTD can be used with the SPICE3 circuit simulation program. The simulated result of a 4-b A/D (analog-to-digital) converter using this model is shown. It is noted that the model can be used with existing SPICE3 device models to simulate the performance of complex circuits that contain resonant tunneling diodes.<<ETX>>

A Current-Mode DC–DC Buck Converter with Efficiency-Optimized Frequency Control and Reconfigurable Compensation

Large input voltage range and wide output current range are usually needed for dc-dc converters. For these input and output conditions, the converters efficiency can be maximized by a proposed method, efficiency-optimized switching-frequency (EOF) control. The optimal switching frequency for maximizing the efficiency is generated by the low-complexity and low-power EOF generator. A reconfigurable compensator is developed for improving the load regulation and the transient response. A piecewise-linear current sensor (PLCS) is employed to reduce controller power loss without sacrificing the sensing accuracy. With the aforementioned three proposed methods, a monolithic current-mode dc-dc buck converter is implemented in a 0.35-μm 3.3-V CMOS process. The measured power-loss reductions and efficiency improvements achieve 16 and 15 mW, and 16% and 1%, both in light and heavy loads, respectively. The load regulation and the transient recovery time are improved by 40 mV and 12 μs, respectively, while the PLCS can reduce 3 mW of power loss. Compared with other published converters in 0.35-μm CMOS process, the implemented converter achieves a higher efficiency of 96.3% and smaller chip area of 0.97 mm.

Low-Cost 14-Bit Current-Steering DAC With a Randomized Thermometer-Coding Method

A dynamic element-matching (DEM) method, i.e., randomized thermometer coding (RTC), for low-cost current-steering digital-to-analog converter (DAC) design is proposed. The proposed RTC method exhibits randomized starting-element selection, consecutive-element selection, and low-element switching activity. It can be used to significantly suppress the harmonic distortion caused by a large mismatch of small-area transistors, and, thus, very low cost DACs can be realized. With the proposed RTC, a 14-bit current-steering DAC is implemented in a 1P6M 0.18- mum 1.8-V CMOS process. The measured spurious-free dynamic range (SFDR) exceeds 80 dB. The measurement results showed that RTC improves the SFDR by more than 16 dB. The DAC has an active area of less than 0.28 mm2. The proposed DAC achieves a smaller active area than state-of-the-art 12- to 14-bit DACs.

A Compact Dynamic-Performance-Improved Current-Steering DAC With Random Rotation-Based Binary-Weighted Selection

Conventional binary-weighted current-steering DACs are generally operated with current groups where each group is binary-weighted and formed with predetermined members of a unit current-source array. This paper proposes a random rotation-based binary-weighted selection (RRBS) that efficiently performs dynamic-element matching (DEM) by randomly rotating the sequence of these units to form new binary-weighted current groups for each DAC output. Without using binary-to-thermometer decoders, RRBS features its simplicity and compactness of DEM realization. Compared to conventional binary-weighted DACs, RRBS DACs are insensitive to the mismatch of small-size current-sources and exhibit better dynamic performance. A 10-bit RRBS DAC is implemented with only 0.034 mm2 in a standard 1P6M 1.8 V 0.18 μm CMOS process. Measured performance achieves >;61 dB spurious-free dynamic range (SFDR) in the Nyquist bandwidth with 500 MS/s, while its active area is less than one-tenth of that required by state-of-the-art 10-bit current steering DACs. To the best of our knowledge, the proposed RRBS implements the smallest area for high-speed current-steering DACs up to now. Its SFDR is also comparable to that of 12-bit published designs. Three popular figures-of-merit (FOMs) are used to compare this design with other state-of-the-art 10-12-bit DACs, with the proposed design performing best with 2 FOMs.

Nyquist-Rate Current-Steering Digital-to-Analog Converters With Random Multiple Data-Weighted Averaging Technique and

In this brief, Nyquist-rate current-steering digital-to-analog converters (DACs) applying the random multiple data-weighted averaging (RMDWA) technique and the QN rotated walk switching scheme are proposed such that high spurious-free dynamic range (SFDR) and small maximum output error can be achieved without calibrations, which are area and power consuming. RMDWA suppresses the harmonics caused by element mismatches to gain high SFDR performance. Furthermore, QN rotated walk can lower the maximum output error when RMDWA and Q N rotated walk are employed simultaneously. Because the benefits of both dynamic element matching technique and switching scheme are obtained by the proposed DAC structure, the proposed structure can deliver smaller maximum output errors than traditional randomization techniques even if a low-cost small-area DAC with poor matching property is adopted

Q^{N}

For current-steering digital-to-analog converters (DACs), a technique utilizing dynamic-element-matching and digital return-to-zero, called DEMDRZ, is proposed to simultaneously suppress the mismatch- and transient-induced nonlinearity. In doing so, the usage of small-sized current sources and switches is possible, and the spurious-free dynamic range (SFDR) and intermodulation distortion (IMD) for high signal frequencies can be improved. With the DEMDRZ technique, a 12-bit compact, low-power, high-speed, high-resolution DAC is implemented in TSMC 40 nm CMOS process. The DAC architecture, circuit, and layout designs are presented. The implemented DAC achieves 70 dB SFDR for signals over the 800 MHz Nyquist bandwidth at 1.6 GS/s and <; -61 dB IMD for signals over the 1.4 GHz Nyquist bandwidth at 2.8 GS/s. Further, it dissipates 40 mW with a single 1.2 V supply. The active area of the DAC is 0.016 mm 2 , which is less than 6% of other state-of-the-art 12-bit current steering DACs. Furthermore, the implemented DAC performs best with three common figure-of-merits (FoMs).