Taizhi Liu

System-level modeling of microprocessor reliability degradation due to BTI and HCI

Negative bias temperature instability (NBTI), positive bias temperature instability (PBTI) and hot carrier injection (HCI) are leading reliability concerns for modern microprocessors. In this paper, a framework is proposed to analyze the impact of NBTI, PBTI and HCI on state-of-art microprocessors and to accurately estimate microprocessor lifetimes due to each wearout mechanism. Our methodology finds the detailed electrical stress and temperature of each device within a microprocessor system running a variety of standard benchmarks. Combining the electrical stress profiles, thermal profiles, and device-level models, we do timing analysis on the critical paths of a microprocessor using our methodology to characterize microprocessor performance degradation due to BTI and HCI. In addition, we study DC noise margins in conventional 6T SRAM cells as a function of BTI and HCI degradation to provide insights on reliability of memories embedded within microprocessors under realistic use conditions.

System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown

Abstract A framework is proposed to analyze system-level reliability and evaluate the lifetimes of state-of-art microprocessors considering the impact of process–voltage–temperature (PVT) variations and device wearout mechanisms, including bias temperature instability (BTI), hot carrier injection (HCI), and gate oxide breakdown (GOBD). This work studies not only the system performance degradation due to each wearout mechanism individually, but also the performance degradation while all these wearout mechanisms happen simultaneously. A unified gate-delay model is developed to combine PVT variations and the aging effect, and then a statistical timing engine is constructed to analyze performance degradations and system lifetimes.

Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements

Negative Bias Temperature Instability (NBTI) is a serious reliability issue for pMOS transistors. Normally, degradation due to NBTI is modeled based on test structure data or ring oscillators embedded within product die. In this paper, we present a new method to determine the NBTI model parameters through I/O circuit measurements. We determine a relationship between Δ Vth and signature signal degradation and fit a model to the simulation results. The signature signal involves the calculation of the degradation in the voltage signature, measured as delay and amplitude shifts. Given an estimate of Δ Vth we find NBTI model parameters. Then, using the NBTI parameters at test conditions, we scale to use conditions and calculate lifetime. The methodology enables the extraction of NBTI model parameters for individual chips, not just for the manufacturing process, and hence it becomes possible to identify chips that are more vulnerable to NBTI.

Comprehensive reliability and aging analysis on SRAMs within microprocessor systems

Abstract A framework is proposed to analyze the impact of both Front End of the Line (FEOL) and Back End of the Line (BEOL) wearout mechanisms on memories embedded within state-of-art microprocessors. Our methodology finds the detailed electrical stress and temperature of each SRAM cell within a memory by running a variety of standard benchmarks. Combining the stress/thermal profiles and the wearout models, the performance degradation of SRAM cells for each wearout mechanism is studied. The lifetimes of the SRAM cells are then obtained when the performance metric degrades to a predefined threshold. The proposed work introduces a method to deal with the large volume of SRAM cells whose stress is non-uniform by partitioning the SRAM cells into different stress states, and generates the lifetime distribution of the memory system due to each wearout mechanism by combining the lifetimes of the cells, whose distributions vary with the stress received. Seven wearout mechanisms have been studied, namely, negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), hot carrier injection (HCI), gate oxide breakdown (GOBD), backend dielectric breakdown (BTDDB), electromigration (EM), and stress-induced voiding (SIV).

Comprehensive Reliability-Aware Statistical Timing Analysis Using a Unified Gate-Delay Model for Microprocessors

A framework is proposed to perform timing analysis of state-of-art microprocessors considering the impact of process-voltage-temperature (PVT) variations and the aging effect, including bias temperature instability (BTI), hot carrier injection (HCI), and time-dependent dielectric breakdown (TDDB). In this work, not only statistical timing analysis (StTA) due to each wearout mechanism is studied individually, but also the performance degradation while all these wearout mechanisms happen simultaneously is analyzed. Moreover, this work takes into account realistic use scenarios which include active, standby, and sleep modes. A unified gate-delay model, which combines both PVT variations and the aging effect, is constructed via a technique called multivariate adaptive regression splines (MARSP). Then a timing engine, which consists of two parts: a block-based analyzer and a path-based analyzer, is built to perform PVT-reliability-aware timing analysis. The accuracy and effectiveness of our framework has been verified on large industrial designs, like the LEON3 microprocessor, through a comparison with SPICE.

System-Level Modeling of Microprocessor Reliability Degradation Due to Bias Temperature Instability and Hot Carrier Injection

Negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), and hot carrier injection (HCI) are leading reliability concerns for modern microprocessors. In this paper, a framework is proposed to analyze the impact of BTI (NBTI and PBTI) and HCI on state-of-art microprocessors and to estimate microprocessor lifetimes due to each wearout mechanism. Our methodology finds the detailed electrical stress and the temperature of each device within a microprocessor system running a variety of standard benchmarks. Combining the electrical stress profiles, thermal profiles, and device-level models, we perform timing analysis on the critical paths of a microprocessor using our methodology to characterize the microprocessor performance degradation due to BTI and HCI and to estimate the lifetime distribution of logic blocks. In addition, we study dc noise margins in conventional 6T SRAM cells as a function of BTI and HCI degradation to estimate memory lifetime distributions. The lifetimes of memory blocks are then combined with the lifetimes of logic blocks to provide an estimate of the system lifetime distribution.

Processor-level reliability simulator for time-dependent gate dielectric breakdown

Time-dependent gate dielectric breakdown (TDDB) is a leading reliability concern for modern microprocessors. In this paper, a framework is proposed to analyze the impact of TDDB on state-of-art microprocessors and to estimate microprocessor lifetimes due to TDDB. Our methodology finds the detailed electrical stress and temperature of each device within a microprocessor system running a variety of standard benchmarks. Combining the electrical stress profiles, thermal profiles, and device-level models, we perform timing analysis on the critical paths of a microprocessor using our methodology to characterize microprocessor performance degradation due to TDDB and to estimate the lifetime distribution of logic blocks. In addition, we study DC noise margins in conventional 6T SRAM cells as a function of TDDB degradation to estimate memory lifetime distributions. The lifetimes of memory blocks are then combined with the lifetimes of logic blocks to provide an estimate of the system lifetime distribution.

SRAM stability analysis for different cache configurations due to Bias Temperature Instability and Hot Carrier Injection

Bias Temperature Instability (BTI) and Hot Carrier Injections (HCI) are two of the main effects that increase a transistors threshold voltage and further cause performance degradations. These two wearout mechanisms affect all transistors, but are especially acute in the SRAM cells of first-level (L1) caches, which are frequently accessed and are critical for microprocessor performance. This work studies the cache lifetimes due to the combined effect of BTI and HCI for different cache configurations, including variation in cache size, associativity, cache line size, and the replacement algorithm. The effect of process variations is also considered. We analyze the reliability (failure probability) and performance (hit rate) of the L1 cache within a LEON3 microprocessor, while the LEON3 is running a set of benchmarks, and we provide essential insights on performance-reliability tradeoffs for cache designers.

Estimation of remaining life using embedded SRAM for wearout parameter extraction

Safety critical systems need methods for chips to monitor their health in the field. This paper proposes to use the embedded SRAM as a monitor of system health. The bit failures are tracked and the cause of each bit failure is diagnosed with on-chip built-in self test (BIST). The wearout model parameters are estimated from the diagnosis results and combined with system wearout simulation data to estimate the remaining lifetime of a system.

The die-to-die calibrated combined model of negative bias temperature instability and gate oxide breakdown from device to system

Abstract In the nanoscale regime, the aggressive scaling of devices is affected by several severe reliability issues, including negative bias temperature instability (NBTI) and gate oxide breakdown (GOBD). Generally, the mathematical models of NBTI and GOBD are derived from device level test structures with accelerated tests. However, although both models are highly dependent on temperature and the gate voltage and both mechanisms are based on the probability of trap generation in the oxide layer, each model has a different impact on circuit performances. In this paper, we use a physical probability model of trap generation for both mechanisms. We first simulate the impact on circuits using process models involving threshold voltage shifts and gate oxide leakage currents for NBTI and GOBD, respectively. Then, we find a relationship between the model parameters and power/ground signal degradation. We find the stress conditions that make each of the two mechanisms dominant in the power/ground signal. We calibrate the NBTI and GOBD model parameters of each chip to experimental results. Hence, it becomes possible to identify chips that are more or less vulnerable to NBTI and GOBD.