Linda Milor

A tutorial introduction to research on analog and mixed-signal circuit testing

Traditionally, work on analog testing has focused on diagnosing faults in board designs. Recently, with increasing levels of integration, not just diagnosing faults, but distinguishing between faulty and good circuits has become a problem. Analog blocks embedded in digital systems may not easily be separately testable. Consequently, many papers have been recently written proposing techniques to reduce the burden of testing analog and mined-signal circuits. This survey attempts to outline some of this recent work, ranging from tools for simulation-based test set development and optimization to built-in self-test (BIST) circuitry.

Detection of catastrophic faults in analog integrated circuits

The IC fabrication process contains several testing stages. Because of the high cost of packaging, the testing stage prior to aging, called wafer probe, is key in reducing the overall manufacturing cost. Typically in this stage, specification tests are performed. Even though specification tests can certainly distinguish a good circuit from all faulty ones, they are expensive, and many types of faulty behavior can be detected by simpler tests. The construction of a set of measurements that detects many faulty circuits before specification testing is described. Bounds on these measurements are specified, and an algorithm for test selection is presented. An example of a possible simple test is a test of DC voltages (i.e., parametric tests). This type of test is defined rigorously, and its effectiveness in detecting faulty circuits is evaluated. >

Minimizing production test time to detect faults in analog circuits

Analog testing is a difficult task without a clearcut methodology. Analog circuits are tested for satisfying their specifications, not for faults. Given the high cost of testing analog specifications, it is proposed that tests for analog circuits should be designed to detect faults. Therefore analog fault modeling is discussed. Based on an analysis of the types of tests needed for different types of faults, algorithms for fault-driven test set selection are presented. A major reduction in testing time should come from reducing the number of specification tests that need to be performed. Hence algorithms are presented for minimizing specification testing time. After specification testing time is minimized, the resulting test sets are supplemented with some simple, possibly non-specification, tests to achieve 100% fault coverage. Examples indicate that fault-driven test set development can lead to drastic reductions in production testing time. >

Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits

In this paper we address both empirically and theoretically the impact of an advanced manufacturing phenomenon on the performance of high-speed digital circuits. Using data collected from an actual state-of-the-art fabrication facility, we conducted a comprehensive characterization of an advanced 0.18-/spl mu/m CMOS process. The measured data revealed a significant systematic, rather than random spatial intrachip variability of MOS gate length, leading to large circuit path delay variation. The delay of the critical path of a combinational logic block varies by as much as 17%, and the global skew is increased by 8%. Thus, a significant timing error and performance loss takes place if variability is not properly addressed. We derive a model, which allows estimating performance degradation for the given circuit and process parameters. We demonstrate explicitly that intrachip Lgate variation has a significant detrimental impact on the overall circuit performance, shifting the entire distribution of clock frequencies toward slower values. This is in striking contrast to the impact of interchip Lgate variation, traditionally considered in statistical circuit analysis, which leads to the variation of chip clock frequencies around the average value. Moreover, analysis shows that the spatial, rather than proximity-dependent systematic Lgate variability, is the main cause of large circuit speed degradation. The degradation is worse for the circuits with a larger number of critical paths and shorter average logic depth. We propose a location-dependent timing analysis methodology that allows mitigation of the detrimental effects of Lgate variability and have developed a tool linking the layout-dependent spatial information to circuit analysis. We discuss the details of practical implementation of the methodology, and provide guidelines for managing design complexity.

Characterization of spatial intrafield gate CD variability, its impact on circuit performance, and spatial mask-level correction

The authors present a comprehensive characterization method applied to the study of the state-of-the-art 18-/spl mu/m CMOS process. Statistical characterization of gate CD reveals a large spatial intrafield component, strongly dependent on the local layout patterns. The authors describe the statistical analysis of this data and demonstrate the need for such comprehensive characterization. They describe the experimental setup of the novel measurement-based characterization approach that is capable of capturing all the relevant CD variation patterns necessary for accurate circuit modeling and statistical design for increased performance and yield. Characterization is based upon an inexpensive electrically based measurement technique. A rigorous statistical analysis of the impact of intrafield variability on circuit performance is undertaken. They show that intrafield CD variation has a significant detrimental effect on the overall circuit performance that may be as high as 25%. Moreover, they demonstrate that the spatial component of gate CD variability, rather than the proximity-dependent component, is predominantly responsible for speed degradation. In order to reduce the degradation of circuit performance and yield, the authors propose a mask-level spatial gate CD correction algorithm to reduce the intrafield and overall variability and provide an analytical model to evaluate the effectiveness of correction for variance reduction. They believe that potentially significant benefits can be achieved through implementation of this compensation technique in the production environment.

Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits

Using data collected from an actual state-of-the-art fabrication facility, we conducted a comprehensive characterization of an advanced 0.18 /spl mu/m CMOS process. The measured data revealed significant systematic, rather than random, spatial intra-chip variability of MOS gate length, leading to large circuit path delay variation. The critical path value of a combinational logic block varies by as much as 17%, and the global skew is increased by 8%. Thus, a significant timing error (/spl sim/25%) and performance loss takes place if variability is not properly addressed. We derive a model, which allows estimating performance degradation for the given circuit and process parameters. Analysis shows that the spatial, rather than proximity-dependent, systematic Lgate variability is the main cause of large circuit speed degradation. The degradation is worse for the circuits with a larger number of critical paths and shorter average logic depth. We propose a location-dependent timing analysis methodology that allows to mitigate the detrimental effects of Lgate variability, and developed a tool linking the layout-dependent spatial information to circuit analysis. We discuss the details of the practical implementation of the methodology, and provide the guidelines for managing the design complexity.

Optimal test set design for analog circuits

Given the high cost of testing analog circuit functionality, it is proposed that tests for analog circuits should be designed to detect faults. An algorithm is presented that reduces functional test sets to only those that are sufficient to find out whether a circuit contains a parametric fault. Examples demonstrate that drastic reductions in test time can be achieved without sacrificing fault coverage.<<ETX>>

Computing parametric yield accurately and efficiently

An algorithm for computing parametric yield is presented. The algorithm uses statistical modeling techniques and takes advantage of incremental knowledge of the problem to reduce significantly the number of simulations needed. Polynomial regression is used to construct simple equations mapping parameters to measurements. These simple polynomial equations can then replace circuit simulations in the Monte Carlo algorithm for computing parametric yield. The algorithm differs from previous statistical modeling algorithms using polynomial regression for three major reasons: first, the random error that is postulated in polynomial regression equations is taken into account when computing parametric yield; second, the variance of the yield is computed; and third, the algorithm is fully automated. Therefore a direct comparison with Monte Carlo methods can be made. Examples indicate that significant speed-ups can be attained over Monte Carlo methods for a large class of problems.<<ETX>>

Analysis of the impact of proximity correction algorithms on circuit performance

Variation in channel length degrades circuit reliability and yield. A common way to compensate for this problem is to increase the mean channel length, which, unfortunately, degrades circuit performance for digital circuits. One source of channel length variation is lithography, during which the line width is influenced by local layout patterns. It is possible to compensate for this effect by resizing transistor gates appropriately on the mask. However, the effectiveness of the correction is limited by constraints such as the mask correction resolution. To determine how to design a good correction scheme with limited resources, we have developed a method to compare different correction algorithms in terms of their impact on the performance of one of the main functional blocks in a state-of-the-art microprocessor. In particular, to evaluate correction algorithms while avoiding the high cost associated with generating multiple mask sets and fabricating product wafers with each of these mask sets, we present a method for predicting the correction results using simulation. Our methodology involves a DRC-based approach for gate resizing, along with critical path simulation for evaluating circuit performance. In-line CD measurement data were used to measure the impact of the proximity effect on transistor channel length. Electrical test results were used to calibrate the device models for circuit simulation.

Logic product speed evaluation and forecasting during the early phases of process technology development using ring oscillator data

During the early stages of the development of a new technology, it is not possible to use product die to optimize parameters for a new technology. At this stage of technology development, integration engineers are forced to rely on test chips to make choices for the future technology. One of the vehicles for optimizing the speed of a technology which is typically available on test chips is ring oscillators. The frequency of oscillation of ring oscillators provides indications of likely product speed and can be measured in the early stages of the development of a new technology. Consequently, they provide us with an early indicator of the probable impact of process changes on circuit performance. However, traditionally, only nominal ring oscillators, with minimal interconnect loading, have been used to estimate the product speed impact of technology changes. As interconnect loading becomes more significant in determining product speed, technology choices based on nominal ring oscillator speed will not be optimal. In this paper, a methodology for using empirical data from ring oscillators, with different frontend and backend loading, to analyze tradeoffs between potential process changes, is presented.